From patchwork Mon Jun 1 19:53:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 1301913 X-Patchwork-Delegate: priyanka.jain@nxp.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=walle.cc header.i=@walle.cc header.a=rsa-sha256 header.s=mail2016061301 header.b=B8TgrPgJ; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49bQsp6qdXz9sWP for ; Tue, 2 Jun 2020 05:56:30 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 3E8B081999; Mon, 1 Jun 2020 21:54:36 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; secure) header.d=walle.cc header.i=@walle.cc header.b="B8TgrPgJ"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 5DF9C808E0; Mon, 1 Jun 2020 21:54:10 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from ssl.serverraum.org (ssl.serverraum.org [IPv6:2a01:4f8:151:8464::1:2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 8135E8120B for ; Mon, 1 Jun 2020 21:53:50 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=michael@walle.cc Received: from apollo.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:6257:18ff:fec4:ca34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 05A5323E40; Mon, 1 Jun 2020 21:53:50 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1591041230; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6jwDglirY6zBR2lm4i0c5Id4cVkwKYg7SpqHMWUPsu0=; b=B8TgrPgJ06Pmy1vg+KX2xXs2Z8iFe8lis0Jfdc/x38B4Xho5wSWxjUnmaNX4oXyuf7SMGN /r8WuFKWRtws4jrWRMu2k8XvW5swBi82gY/61DNfGEymcnB1onTM4dRq0N0Wzsb1FLoWib YGTtkNteo+2fefrnuc+MGJLURwKTPtI= From: Michael Walle To: u-boot@lists.denx.de Cc: Udit Kumar , Meenakshi Aggarwal , Prabhakar Kushwaha , Priyanka Jain , Tom Rini , Heinrich Schuchardt , Michael Walle Subject: [PATCH v2 11/13] armv8: layerscape: clean exported symbols in spintable.S Date: Mon, 1 Jun 2020 21:53:34 +0200 Message-Id: <20200601195336.3237-12-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200601195336.3237-1-michael@walle.cc> References: <20200601195336.3237-1-michael@walle.cc> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean Add a new variable secondary_boot_code_start, which holds a pointer to the start of the spin table code. This will help to relocate the code section. While at it, move the size variable from the end to the beginning so there is a common section for the variables. Remove any other symbols. Signed-off-by: Michael Walle --- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 9 +++---- arch/arm/cpu/armv8/fsl-layerscape/mp.c | 4 ++- arch/arm/cpu/armv8/fsl-layerscape/spintable.S | 26 ++++++++++--------- arch/arm/include/asm/arch-fsl-layerscape/mp.h | 6 ++--- 4 files changed, 24 insertions(+), 21 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 9c7546028a..9c1e0c76f3 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -54,7 +54,6 @@ void ft_fixup_cpu(void *blob) fdt32_t *reg; int addr_cells; u64 val, core_id; - size_t *boot_code_size = &(__secondary_boot_code_size); u32 mask = cpu_pos_mask(); int off_prev = -1; @@ -145,11 +144,11 @@ remove_psci_node: "cpu", 4); } - fdt_add_mem_rsv(blob, (uintptr_t)&secondary_boot_code, - *boot_code_size); + fdt_add_mem_rsv(blob, (uintptr_t)secondary_boot_code_start, + secondary_boot_code_size); #if CONFIG_IS_ENABLED(EFI_LOADER) - efi_add_memory_map((uintptr_t)&secondary_boot_code, *boot_code_size, - EFI_RESERVED_MEMORY_TYPE); + efi_add_memory_map((uintptr_t)secondary_boot_code_start, + secondary_boot_code_size, EFI_RESERVED_MEMORY_TYPE); #endif } #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index 753215add0..d50c5a437b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -15,12 +15,14 @@ #include #include "cpu.h" #include +#include DECLARE_GLOBAL_DATA_PTR; void *get_spin_tbl_addr(void) { - return &__spin_table; + /* the spin table is at the beginning */ + return secondary_boot_code_start; } void update_os_arch_secondary_cores(uint8_t os_arch) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spintable.S b/arch/arm/cpu/armv8/fsl-layerscape/spintable.S index 0e38cd009b..f082e10231 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spintable.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/spintable.S @@ -10,23 +10,28 @@ #include #include - .align 3 - .global secondary_boot_addr +.align 3 +.global secondary_boot_addr secondary_boot_addr: - .quad secondary_boot_func + .quad __secondary_boot_func + +.global secondary_boot_code_start +secondary_boot_code_start: + .quad __secondary_boot_code_start +.global secondary_boot_code_size +secondary_boot_code_size: + .quad __secondary_boot_code_end - __secondary_boot_code_start /* Using 64 bit alignment since the spin table is accessed as data */ .align 3 - .global secondary_boot_code /* Secondary Boot Code starts here */ -secondary_boot_code: - .global __spin_table +__secondary_boot_code_start: __spin_table: .space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE .align 2 -ENTRY(secondary_boot_func) +ENTRY(__secondary_boot_func) /* * MPIDR_EL1 Fields: * MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1) @@ -100,7 +105,7 @@ cpu_is_le: ldr x5, =ES_TO_AARCH64 bl secondary_switch_to_el2 -ENDPROC(secondary_boot_func) +ENDPROC(__secondary_boot_func) ENTRY(secondary_switch_to_el2) switch_el x6, 1f, 0f, 0f @@ -146,8 +151,5 @@ ENDPROC(secondary_switch_to_el1) .global __real_cntfrq __real_cntfrq: .quad COUNTER_FREQUENCY - .globl __secondary_boot_code_size - .type __secondary_boot_code_size, %object /* Secondary Boot Code ends here */ -__secondary_boot_code_size: - .quad .-secondary_boot_code +__secondary_boot_code_end: diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mp.h b/arch/arm/include/asm/arch-fsl-layerscape/mp.h index 3b470439bd..faac8f1128 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/mp.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h @@ -32,10 +32,10 @@ #define id_to_core(x) ((x & 3) | (x >> 6)) #ifndef __ASSEMBLY__ -extern u64 __spin_table[]; extern u64 __real_cntfrq; -extern u64 *secondary_boot_code; -extern size_t __secondary_boot_code_size; +extern void *secondary_boot_addr; +extern void *secondary_boot_code_start; +extern size_t secondary_boot_code_size; #ifdef CONFIG_MP int fsl_layerscape_wake_seconday_cores(void); #else