From patchwork Fri May 29 06:03:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pragnesh Patel X-Patchwork-Id: 1300383 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256 header.s=selector1 header.b=YlN+VEg5; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49YDd20Mswz9sSn for ; Fri, 29 May 2020 16:07:49 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 1734981CB4; Fri, 29 May 2020 08:05:53 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="YlN+VEg5"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 195B981CB4; Fri, 29 May 2020 08:05:24 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FORGED_SPF_HELO,MSGID_FROM_MTA_HEADER, SPF_HELO_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.2 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2061c.outbound.protection.outlook.com [IPv6:2a01:111:f400:fe5a::61c]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 875D481C9C for ; Fri, 29 May 2020 08:05:19 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pragnesh.patel@sifive.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=PJzUxDpgX0VyTPgYHK4d1UgDwbd3H7iA6zfHg9qsHqBrF/cXk1W65TJkpdFbMfay28hzTu+jaAT51WN+7Fm/Y5HdexdTnew0CuO9VcbWEnBR/6lEBw0MGdjzYfcH6dhkPnlWBH+0lumtxzj+as8hLsJqII3MgJ9a1XNlnEFCOw5Fxvntm2/RB1PQtOM6/8bwMww6tf9Tpb2g3L86YtpeF359CCuPMkniEIUADDkNk2jEqpyOLcOXiWQtD90VdQjezzZuNVFbS3jx6OS1s3tx78kWfeXKg0XEnIBtyQKhtMmF1cry8SW/VqFadyNw9WrKKbPPSod0rcmKfdSAwky+HA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=v/WLDuCHaJgJeoG04FMIn+FWSLuGTr5AG2n2xj42xjs=; b=fZcNKlByqLQXccQmDdOAYlYJtU//OHilTFbDUpMqOP/IAyvc6dlXcxw9dVdH37r1uS+/kp+h7DWQEiR9dTtcPuTCk7qSoxRqP1EkvsWXCjXC4vVpnCvJr6JDbqaVqMCSlI8lxjfL7QzMAeyDSPDv6N0A4enJqOWEJSKdQfxHcdZdK/38wQZ4l+qf18MgJsmenxb9yTJVRsyWWv5zKESfgHIxB0+znEFlKQjwNgc/kVDoqUm1a4mPyIdcDK6qhaMECjgS66YmCmf4Ij5ARNQ5ZE7MmuwHSXpqS9pfsZ86SqdRPR140/3yBrr9dPQkNwk8Zf1N7hXfLFRgh/eEnhtfwQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=sifive.com; dmarc=pass action=none header.from=sifive.com; dkim=pass header.d=sifive.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=v/WLDuCHaJgJeoG04FMIn+FWSLuGTr5AG2n2xj42xjs=; b=YlN+VEg5ICEbsOhWp8alRiqYbOe4lz75S7zZ7V8MmwSLAkvj2gTskBuI7Us+dygmYeABqKleuNoTL5sahAiOlsKYsb5xKhN1KV74H6fa+kcQWQh01jnyJqH3/ApGSmoNXDLT+CRD/A6WAl0x0n55dWfKlkJ9AoOE016v5lVE24c= Authentication-Results: lists.denx.de; dkim=none (message not signed) header.d=none;lists.denx.de; dmarc=none action=none header.from=sifive.com; Received: from MN2PR13MB2797.namprd13.prod.outlook.com (2603:10b6:208:f2::30) by MN2PR13MB3135.namprd13.prod.outlook.com (2603:10b6:208:135::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3066.7; Fri, 29 May 2020 06:05:17 +0000 Received: from MN2PR13MB2797.namprd13.prod.outlook.com ([fe80::e50d:b981:362f:58ed]) by MN2PR13MB2797.namprd13.prod.outlook.com ([fe80::e50d:b981:362f:58ed%5]) with mapi id 15.20.3045.015; Fri, 29 May 2020 06:05:17 +0000 From: Pragnesh Patel To: u-boot@lists.denx.de Cc: atish.patra@wdc.com, palmerdabbelt@google.com, bmeng.cn@gmail.com, paul.walmsley@sifive.com, jagan@amarulasolutions.com, anup.patel@wdc.com, sagar.kadam@sifive.com, rick@andestech.com, Pragnesh Patel , Palmer Dabbelt Subject: [PATCH v13 15/19] riscv: sifive: fu540: add SPL configuration Date: Fri, 29 May 2020 11:33:35 +0530 Message-Id: <20200529060340.26708-16-pragnesh.patel@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200529060340.26708-1-pragnesh.patel@sifive.com> References: <20200529060340.26708-1-pragnesh.patel@sifive.com> X-ClientProxiedBy: LO2P265CA0079.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:8::19) To MN2PR13MB2797.namprd13.prod.outlook.com (2603:10b6:208:f2::30) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sachinj2-OptiPlex-7010.open-silicon.com (114.143.65.226) by LO2P265CA0079.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:8::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3045.21 via Frontend Transport; Fri, 29 May 2020 06:05:14 +0000 X-Mailer: git-send-email 2.17.1 X-Originating-IP: [114.143.65.226] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: dbc0156b-0d68-4bd3-278c-08d80396426e X-MS-TrafficTypeDiagnostic: MN2PR13MB3135: X-LD-Processed: 22f88e9d-ae0d-4ed9-b984-cdc9be1529f1,ExtAddr X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:16; X-Forefront-PRVS: 04180B6720 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: guxTF9VkEe9rtb0de9Pez+AhzJec8e1gGg5Y1kncA7ysHxplbMsg7bmbOcDNa5t6Ft5p7D7qN3mp8yuHg9HwYYq7Bmz1nXYzutyB0OIktOADPJI1y8WOIfbWkkDp0m3S02TzQKyIDmayND9IRWhmE5jmD6xABvgxAaWMtQcpTdDo/eJcDmzcDHhpfMDgmOvOFpSPBnO7XXSAz4dMkoUxRbZDqptVdCtRS5q7rsNBniB04+yFnDVdYg+ChsEn3naqtLUrBcKAfmQTZbSjWozjKC4fWpwiVVjXZEzigHSXVYMn2M5sY1bN5UwVybJAWDq/3GTV7FbCyilFd+j2QFlWU+dOizhLOqHYsxtLrpY67MOqSD0k8N8mYoxWGyyTwwqcfHPq9nk90CbKXAdj0GRXeQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:MN2PR13MB2797.namprd13.prod.outlook.com; PTR:; CAT:NONE; SFTY:; SFS:(396003)(39850400004)(136003)(376002)(366004)(346002)(956004)(44832011)(26005)(6506007)(2906002)(52116002)(316002)(5660300002)(1006002)(6666004)(1076003)(54906003)(86362001)(36756003)(8676002)(66476007)(66556008)(2616005)(6916009)(16526019)(186003)(478600001)(8936002)(83380400001)(4326008)(66946007)(6512007)(6486002); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: iScBEYWEmO4VMVo/AzIH39r0oqs/7v+uoEc73JWsMCGMc1YacSc89qDKuaBFijUaTetBxJeZOpxxNnF0xc6ULR0kqDB+JuCKgwbmeaY4klRnng7TWIRO1AHMbs1Jew4tscX/7dvAPEau4TyJys97+N5cz8kFGNNQrXc1nbbdDWcvPGylQNbD85SmHdArzAApt7xPrYM855LJXmlogZ88XKWFgUorVxMjo8ddI8pZxJ4HpZEAzf6WH1gitKF7LPHldXfWt388y38MgEg6reMQbcix70FAnOH2xa8W90is7NyipBcIyaEtB7CBJEp8L+nBz74ht1qbDjpQ1RREnZZJax6ILLrOUDKRdQ4YiLFNAKjyklTSHF9KRKr6uEBor5aaW0GlRPvKkfmA99M/Ju/iLnLRggNdWhifiaoFtMEZShgDnaKoveXQnBx/hTDwvoWhPmZjzGs8I9vXWgrZicYgjultZohpqiFQTOeJ6rmTslI= X-OriginatorOrg: sifive.com X-MS-Exchange-CrossTenant-Network-Message-Id: dbc0156b-0d68-4bd3-278c-08d80396426e X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 May 2020 06:05:17.0576 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 22f88e9d-ae0d-4ed9-b984-cdc9be1529f1 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: KCyyw9Lf3rwyuhtpBRGMor38RRADVE3Ut6IuVM9M9zjtZk4ESXRhDsq2mIhCoglWcYixmX+knQThWRsYD4dlgyr6OAVFMDxOolmo0IL8BL0= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR13MB3135 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean Add a support for SPL which will boot from L2 LIM (0x0800_0000) and then SPL will boot U-Boot FIT image (OpenSBI FW_DYNAMIC + u-boot.bin) from MMC boot devices. SPL related code is leveraged from FSBL (https://github.com/sifive/freedom-u540-c000-bootloader.git) Signed-off-by: Pragnesh Patel Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Jagan Teki Tested-by: Jagan Teki --- arch/riscv/cpu/fu540/Makefile | 4 + arch/riscv/cpu/fu540/spl.c | 23 ++++++ .../dts/hifive-unleashed-a00-u-boot.dtsi | 5 ++ arch/riscv/include/asm/arch-fu540/spl.h | 14 ++++ board/sifive/fu540/Kconfig | 10 ++- board/sifive/fu540/Makefile | 4 + board/sifive/fu540/fu540.c | 21 ++++++ board/sifive/fu540/spl.c | 74 +++++++++++++++++++ include/configs/sifive-fu540.h | 18 +++++ 9 files changed, 172 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/cpu/fu540/spl.c create mode 100644 arch/riscv/include/asm/arch-fu540/spl.h create mode 100644 board/sifive/fu540/spl.c diff --git a/arch/riscv/cpu/fu540/Makefile b/arch/riscv/cpu/fu540/Makefile index 44700d998c..043fb961a5 100644 --- a/arch/riscv/cpu/fu540/Makefile +++ b/arch/riscv/cpu/fu540/Makefile @@ -3,5 +3,9 @@ # Copyright (C) 2020 SiFive, Inc # Pragnesh Patel +ifeq ($(CONFIG_SPL_BUILD),y) +obj-y += spl.o +else obj-y += dram.o obj-y += cpu.o +endif diff --git a/arch/riscv/cpu/fu540/spl.c b/arch/riscv/cpu/fu540/spl.c new file mode 100644 index 0000000000..a2034e933f --- /dev/null +++ b/arch/riscv/cpu/fu540/spl.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 SiFive, Inc + * Pragnesh Patel + */ + +#include +#include + +int soc_spl_init(void) +{ + int ret; + struct udevice *dev; + + /* DDR init */ + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return ret; + } + + return 0; +} diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi index 9787332bf1..303806454b 100644 --- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi @@ -4,6 +4,7 @@ */ #include "fu540-c000-u-boot.dtsi" +#include "fu540-hifive-unleashed-a00-ddr.dtsi" / { aliases { @@ -26,3 +27,7 @@ u-boot,dm-spl; }; }; + +&gpio { + u-boot,dm-spl; +}; diff --git a/arch/riscv/include/asm/arch-fu540/spl.h b/arch/riscv/include/asm/arch-fu540/spl.h new file mode 100644 index 0000000000..0c188be747 --- /dev/null +++ b/arch/riscv/include/asm/arch-fu540/spl.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 SiFive, Inc. + * + * Authors: + * Pragnesh Patel + */ + +#ifndef _SPL_SIFIVE_H +#define _SPL_SIFIVE_H + +int soc_spl_init(void); + +#endif /* _SPL_SIFIVE_H */ diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig index eb5ba3123d..4a77a2a37b 100644 --- a/board/sifive/fu540/Kconfig +++ b/board/sifive/fu540/Kconfig @@ -13,12 +13,20 @@ config SYS_CONFIG_NAME default "sifive-fu540" config SYS_TEXT_BASE + default 0x80200000 if SPL default 0x80000000 if !RISCV_SMODE default 0x80200000 if RISCV_SMODE +config SPL_TEXT_BASE + default 0x08000000 + +config SPL_OPENSBI_LOAD_ADDR + default 0x80000000 + config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select GENERIC_RISCV + select SIFIVE_FU540 + select SUPPORT_SPL select RAM select SPL_RAM if SPL imply CMD_DHCP diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile index 6e1862c475..b05e2f5807 100644 --- a/board/sifive/fu540/Makefile +++ b/board/sifive/fu540/Makefile @@ -3,3 +3,7 @@ # Copyright (c) 2019 Western Digital Corporation or its affiliates. obj-y += fu540.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c index ef2c40da27..fa705dea71 100644 --- a/board/sifive/fu540/fu540.c +++ b/board/sifive/fu540/fu540.c @@ -14,6 +14,7 @@ #include #include #include +#include /* * This define is a value used for error/unknown serial. @@ -117,3 +118,23 @@ int board_init(void) return 0; } + +#ifdef CONFIG_SPL +u32 spl_boot_device(void) +{ +#ifdef CONFIG_SPL_MMC_SUPPORT + return BOOT_DEVICE_MMC1; +#else + puts("Unknown boot device\n"); + hang(); +#endif +} +#endif + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* boot using first FIT config */ + return 0; +} +#endif diff --git a/board/sifive/fu540/spl.c b/board/sifive/fu540/spl.c new file mode 100644 index 0000000000..55325cf99d --- /dev/null +++ b/board/sifive/fu540/spl.c @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 SiFive, Inc + * + * Authors: + * Pragnesh Patel + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define GEM_PHY_RESET SIFIVE_GENERIC_GPIO_NR(0, 12) + +int init_clk_and_ddr(void) +{ + int ret; + + ret = soc_spl_init(); + if (ret) { + debug("FU540 SPL init failed: %d\n", ret); + return ret; + } + + /* + * GEMGXL init VSC8541 PHY reset sequence; + * leave pull-down active for 2ms + */ + udelay(2000); + ret = gpio_request(GEM_PHY_RESET, "gem_phy_reset"); + if (ret) { + debug("gem_phy_reset gpio request failed: %d\n", ret); + return ret; + } + + /* Set GPIO 12 (PHY NRESET) */ + ret = gpio_direction_output(GEM_PHY_RESET, 1); + if (ret) { + debug("gem_phy_reset gpio direction set failed: %d\n", ret); + return ret; + } + + udelay(1); + + /* Reset PHY again to enter unmanaged mode */ + gpio_set_value(GEM_PHY_RESET, 0); + udelay(1); + gpio_set_value(GEM_PHY_RESET, 1); + mdelay(15); + + return 0; +} + +void board_init_f(ulong dummy) +{ + int ret; + + ret = spl_early_init(); + if (ret) + panic("spl_early_init() failed: %d\n", ret); + + arch_cpu_init_dm(); + + preloader_console_init(); + + ret = init_clk_and_ddr(); + if (ret) + panic("init_clk_and_ddr() failed: %d\n", ret); +} diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h index 2756ed5a77..ef3ae9b650 100644 --- a/include/configs/sifive-fu540.h +++ b/include/configs/sifive-fu540.h @@ -11,6 +11,22 @@ #include +#ifdef CONFIG_SPL + +#define CONFIG_SPL_MAX_SIZE 0x00100000 +#define CONFIG_SPL_BSS_START_ADDR 0x85000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 + +#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x84000000 + +#define CONFIG_SPL_STACK (0x08000000 + 0x001D0000 - \ + GENERATED_GBL_DATA_SIZE) + +#endif + #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) @@ -24,6 +40,7 @@ /* Environment options */ +#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(DHCP, dhcp, na) @@ -43,5 +60,6 @@ #define CONFIG_PREBOOT \ "setenv fdt_addr ${fdtcontroladdr};" \ "fdt addr ${fdtcontroladdr};" +#endif #endif /* __CONFIG_H */