From patchwork Wed May 20 05:33:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kongou Hikari X-Patchwork-Id: 1294243 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=nucleisys.com Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49Rqtt1nRjz9sPK for ; Wed, 20 May 2020 21:16:05 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id ADD6F81E8E; Wed, 20 May 2020 13:15:17 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=nucleisys.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 0C9E181E2C; Wed, 20 May 2020 07:36:08 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from out28-197.mail.aliyun.com (out28-197.mail.aliyun.com [115.124.28.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id AD33E81E12 for ; Wed, 20 May 2020 07:35:55 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=nucleisys.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=hikari@nucleisys.com X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436412|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0149679-7.78064e-06-0.985024; FP=13609309071410268376|2|2|2|0|-1|-1|-1; HT=e02c03311; MF=hikari@nucleisys.com; NM=1; PH=DS; RN=1; RT=1; SR=0; TI=SMTPD_---.Hb.sdUO_1589952932; Received: from softserver(mailfrom:hikari@nucleisys.com fp:SMTPD_---.Hb.sdUO_1589952932) by smtp.aliyun-inc.com(10.147.40.2); Wed, 20 May 2020 13:35:32 +0800 From: Kongou Hikari To: u-boot@lists.denx.de Subject: [PATCH 1/2] serial: Add riscv_sbi console support Date: Wed, 20 May 2020 13:33:30 +0800 Message-Id: <20200520053331.27757-1-hikari@nucleisys.com> X-Mailer: git-send-email 2.17.1 X-Mailman-Approved-At: Wed, 20 May 2020 13:15:05 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean - This patch supports debug serial and console from SBI syscall. Signed-off-by: Kongou Hikari --- drivers/serial/Kconfig | 17 +++++ drivers/serial/Makefile | 1 + drivers/serial/serial_riscv_sbi.c | 104 ++++++++++++++++++++++++++++++ 3 files changed, 122 insertions(+) create mode 100644 drivers/serial/serial_riscv_sbi.c diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 90e3983170..60dcf9bc9a 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -388,12 +388,20 @@ config DEBUG_UART_MTK driver will be available until the real driver model serial is running. + +config DEBUG_UART_RISCV_SBI + bool "RISC-V SBI CONSOLE" + depends on RISCV_SBI_CONSOLE + help + Select this to enable a debug UART using RISC-V SBI console driver. + endchoice config DEBUG_UART_BASE hex "Base address of UART" depends on DEBUG_UART default 0 if DEBUG_UART_SANDBOX + default 0 if DEBUG_UART_RISCV_SBI help This is the base address of your UART for memory-mapped UARTs. @@ -404,6 +412,7 @@ config DEBUG_UART_CLOCK int "UART input clock" depends on DEBUG_UART default 0 if DEBUG_UART_SANDBOX + default 0 if DEBUG_UART_RISCV_SBI help The UART input clock determines the speed of the internal UART circuitry. The baud rate is derived from this by dividing the input @@ -481,6 +490,14 @@ config ALTERA_JTAG_UART_BYPASS output will wait forever until a JTAG terminal is connected. If you not are sure, say Y. +config RISCV_SBI_CONSOLE + bool "RISC-V SBI console support" + depends on RISCV + help + This enables support for console via RISC-V SBI calls. + + If you don't know what do to here, say Y. + config ALTERA_UART bool "Altera UART support" depends on DM_SERIAL diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index e4a92bbbb7..15b2a3ea6f 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -46,6 +46,7 @@ obj-$(CONFIG_MXC_UART) += serial_mxc.o obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o obj-$(CONFIG_MESON_SERIAL) += serial_meson.o obj-$(CONFIG_INTEL_MID_SERIAL) += serial_intel_mid.o +obj-$(CONFIG_RISCV_SBI_CONSOLE) += serial_riscv_sbi.o ifdef CONFIG_SPL_BUILD obj-$(CONFIG_ROCKCHIP_SERIAL) += serial_rockchip.o endif diff --git a/drivers/serial/serial_riscv_sbi.c b/drivers/serial/serial_riscv_sbi.c new file mode 100644 index 0000000000..add11be04e --- /dev/null +++ b/drivers/serial/serial_riscv_sbi.c @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2008 David Gibson, IBM Corporation + * Copyright (C) 2012 Regents of the University of California + * Copyright (C) 2020 Nuclei System Technologies + * Copyright (C) 2020 Ruigang Wan + */ + +#include +#include +#include +#include +#include + +#include + + +#ifdef CONFIG_DEBUG_UART_RISCV_SBI + +#include + + +static inline void _debug_uart_init(void) +{ + //Nothing +} + +static inline void _debug_uart_putc(int ch) +{ + sbi_console_putchar(ch); +} + +DEBUG_UART_FUNCS + +#endif + +static int sbi_tty_pending_char = -1; + +static int sbi_tty_put(struct udevice *dev, const char ch) +{ + + sbi_console_putchar(ch); + + return 0; +} + +static int sbi_tty_get(struct udevice *dev) +{ + int c; + if (sbi_tty_pending_char != -1) + { + c = sbi_tty_pending_char; + sbi_tty_pending_char = -1; + } + else + { + c = sbi_console_getchar(); + if (c < 0) + return -EAGAIN; + } + + return c; +} + +static int sbi_tty_setbrg(struct udevice *dev, int baudrate) +{ + return 0; +} + +static int sbi_tty_pending(struct udevice *dev, bool input) +{ + int c; + if (input) + { + if (sbi_tty_pending_char != -1) + return 1; + + c = sbi_console_getchar(); + if(c < 0) + return 0; + sbi_tty_pending_char = c; + return 1; + } + return 0; +} + +static const struct udevice_id serial_riscv_sbi_ids[] = { + { .compatible = "sbi,console" }, + { } +}; + +const struct dm_serial_ops serial_riscv_sbi_ops = { + .putc = sbi_tty_put, + .pending = sbi_tty_pending, + .getc = sbi_tty_get, + .setbrg = sbi_tty_setbrg, +}; + +U_BOOT_DRIVER(serial_riscv_sbi) = { + .name = "serial_riscv_sbi", + .id = UCLASS_SERIAL, + .of_match = serial_riscv_sbi_ids, + .ops = &serial_riscv_sbi_ops, +};