From patchwork Mon May 18 11:48:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ioana Ciornei X-Patchwork-Id: 1292488 X-Patchwork-Delegate: priyanka.jain@nxp.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49QckL30RVz9sRN for ; Mon, 18 May 2020 21:49:30 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id B3E6A81CB9; Mon, 18 May 2020 13:48:56 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=nxp.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 32D3681CA8; Mon, 18 May 2020 13:48:48 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id B07638164F for ; Mon, 18 May 2020 13:48:40 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ioana.ciornei@nxp.com Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 04E581A0AFD; Mon, 18 May 2020 13:48:40 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id EB6AD1A0AFA; Mon, 18 May 2020 13:48:39 +0200 (CEST) Received: from fsr-ub1864-126.ea.freescale.net (fsr-ub1864-126.ea.freescale.net [10.171.82.212]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id A2E4E203C0; Mon, 18 May 2020 13:48:39 +0200 (CEST) From: Ioana Ciornei To: priyanka.jain@nxp.com, u-boot@lists.denx.de Cc: Ioana Ciornei Subject: [PATCH v3 2/3] arm: dts: ls2080aqds: add CONFIG_MULTI_DTB_FIT support Date: Mon, 18 May 2020 14:48:36 +0300 Message-Id: <20200518114837.25020-3-ioana.ciornei@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200518114837.25020-1-ioana.ciornei@nxp.com> References: <20200518114837.25020-1-ioana.ciornei@nxp.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ioana.ciornei@nxp.com Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean Add support for selecting the appropriate DTS file depending on the SERDES protocol used. The fsl-ls2080a-qds DTS will be used by default if there isn't a DTS file specifically made for the current SERDES protocol. This patch adds the necessary DPMAC nodes (DPMAC 1-8) for protocol 42 (0x2A) on SD#1. Also, in case CONFIG_DM_ETH and CONFIG_MULTI_DTB_FIT are enabled implement the board_fit_config_name_match() function in order to choose the appropriate DTS. Signed-off-by: Ioana Ciornei --- Changes in v3: - none arch/arm/dts/Makefile | 1 + arch/arm/dts/fsl-ls2080a-qds-42-x.dts | 16 ++++ arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi | 48 ++++++++++++ arch/arm/dts/fsl-ls2080a-qds.dts | 72 +----------------- arch/arm/dts/fsl-ls2080a-qds.dtsi | 77 +++++++++++++++++++ board/freescale/ls2080aqds/eth.c | 97 ++++++++++++++++++++++++ 6 files changed, 241 insertions(+), 70 deletions(-) create mode 100644 arch/arm/dts/fsl-ls2080a-qds-42-x.dts create mode 100644 arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi create mode 100644 arch/arm/dts/fsl-ls2080a-qds.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 5be6acb108be..7a766924e98d 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -374,6 +374,7 @@ dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \ ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \ ls1021a-iot-duart.dtb ls1021a-tsn.dtb dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ + fsl-ls2080a-qds-42-x.dtb \ fsl-ls2080a-rdb.dtb \ fsl-ls2081a-rdb.dtb \ fsl-ls2088a-rdb-qspi.dtb \ diff --git a/arch/arm/dts/fsl-ls2080a-qds-42-x.dts b/arch/arm/dts/fsl-ls2080a-qds-42-x.dts new file mode 100644 index 000000000000..bd46c395d45c --- /dev/null +++ b/arch/arm/dts/fsl-ls2080a-qds-42-x.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS2080AQDS device tree source for SERDES protocol 42.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-ls2080a-qds-sd1-42.dtsi" + +/ { + model = "NXP Layerscape LS2080AQDS Board (DTS 42-x)"; + compatible = "fsl,ls2080a-qds", "fsl,ls2080a"; +}; diff --git a/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi b/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi new file mode 100644 index 000000000000..ccbb5de1eaef --- /dev/null +++ b/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS2080aQDS device tree source for SERDES block #1 - protocol 42 (0x2a) + * + * Copyright 2020 NXP + */ + +#include "fsl-ls2080a-qds.dtsi" + +&dpmac1 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac2 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac3 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac4 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac5 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac6 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac7 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac8 { + status = "okay"; + phy-connection-type = "xfi"; +}; diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b/arch/arm/dts/fsl-ls2080a-qds.dts index f91a48d9fddb..a1196f929287 100644 --- a/arch/arm/dts/fsl-ls2080a-qds.dts +++ b/arch/arm/dts/fsl-ls2080a-qds.dts @@ -1,13 +1,13 @@ // SPDX-License-Identifier: GPL-2.0+ OR X11 /* - * Freescale ls2080a QDS board device tree source + * Freescale ls2080a QDS defaul board device tree source * * Copyright 2013-2015 Freescale Semiconductor, Inc. */ /dts-v1/; -#include "fsl-ls2080a.dtsi" +#include "fsl-ls2080a-qds.dtsi" / { model = "Freescale Layerscape 2080a QDS Board"; @@ -18,71 +18,3 @@ spi1 = &dspi; }; }; - -&i2c0 { - status = "okay"; - pca9547@77 { - compatible = "nxp,pca9547"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x00>; - rtc@68 { - compatible = "dallas,ds3232"; - reg = <0x68>; - }; - }; - }; -}; - -&dspi { - bus-num = <0>; - status = "okay"; - - dflash0: n25q128a { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <3000000>; - spi-cpol; - spi-cpha; - reg = <0>; - }; - dflash1: sst25wf040b { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <3000000>; - spi-cpol; - spi-cpha; - reg = <1>; - }; - dflash2: en25s64 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <3000000>; - spi-cpol; - spi-cpha; - reg = <2>; - }; -}; - -&qspi { - status = "okay"; - - s25fs256s0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - }; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm/dts/fsl-ls2080a-qds.dtsi b/arch/arm/dts/fsl-ls2080a-qds.dtsi new file mode 100644 index 000000000000..cb7851f2cc01 --- /dev/null +++ b/arch/arm/dts/fsl-ls2080a-qds.dtsi @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Freescale ls2080a QDS common device tree source + * + * Copyright 2013-2015 Freescale Semiconductor, Inc. + * Copyright 2020 NXP + */ + +#include "fsl-ls2080a.dtsi" + +&i2c0 { + status = "okay"; + pca9547@77 { + compatible = "nxp,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x00>; + rtc@68 { + compatible = "dallas,ds3232"; + reg = <0x68>; + }; + }; + }; +}; + +&dspi { + bus-num = <0>; + status = "okay"; + + dflash0: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; + dflash1: sst25wf040b { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <1>; + }; + dflash2: en25s64 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <2>; + }; +}; + +&qspi { + status = "okay"; + + s25fs256s0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + }; +}; + +&sata { + status = "okay"; +}; diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c index 2b1b106b0732..0d6eec377f84 100644 --- a/board/freescale/ls2080aqds/eth.c +++ b/board/freescale/ls2080aqds/eth.c @@ -989,3 +989,100 @@ void reset_phy(void) mc_env_boot(); } #endif /* CONFIG_RESET_PHY_R */ + +#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT) + +/* Structure to hold SERDES protocols supported in case of + * CONFIG_DM_ETH enabled (network interfaces are described in the DTS). + * + * @serdes_block: the index of the SERDES block + * @serdes_protocol: the decimal value of the protocol supported + * @dts_needed: DTS notes describing the current configuration are needed + * + * When dts_needed is true, the board_fit_config_name_match() function + * will try to exactly match the current configuration of the block with a DTS + * name provided. + */ +static struct serdes_configuration { + u8 serdes_block; + u32 serdes_protocol; + bool dts_needed; +} supported_protocols[] = { + /* Serdes block #1 */ + {1, 42, true}, + + /* Serdes block #2 */ + {2, 65, false}, +}; + +#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols) + +static bool protocol_supported(u8 serdes_block, u32 protocol) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) + return true; + } + + return false; +} + +static void get_str_protocol(u8 serdes_block, u32 protocol, char *str) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) { + if (serdes_conf.dts_needed == true) + sprintf(str, "%u", protocol); + else + sprintf(str, "x"); + return; + } + } +} + +int board_fit_config_name_match(const char *name) +{ + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 rcw_status = in_le32(&gur->rcwsr[28]); + char srds_s1_str[2], srds_s2_str[2]; + u32 srds_s1, srds_s2; + char expected_dts[100]; + + srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; + + srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK; + srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; + + /* Check for supported protocols. The default DTS will be used + * in this case + */ + if (!protocol_supported(1, srds_s1) || + !protocol_supported(2, srds_s2)) + return -1; + + get_str_protocol(1, srds_s1, srds_s1_str); + get_str_protocol(2, srds_s2, srds_s2_str); + + printf("expected_dts %s\n", expected_dts); + sprintf(expected_dts, "fsl-ls2080a-qds-%s-%s", + srds_s1_str, srds_s2_str); + + if (!strcmp(name, expected_dts)) + return 0; + + printf("this is not!\n"); + return -1; +} + +#endif