diff mbox series

[V2,2/7] driver: ddr: imx: correct the pwrctl setting of selfref_en on imx8m

Message ID 20200512015051.3486-3-peng.fan@nxp.com
State Changes Requested
Delegated to: Stefano Babic
Headers show
Series imx: drivers: ddr: ddr driver update | expand

Commit Message

Peng Fan May 12, 2020, 1:50 a.m. UTC 
From: Jacky Bai <ping.bai@nxp.com>

The 'selfref_en' should be bit'0', so correct the setting to
enable the auto self-refresh.

Reviewed-by: Jian Li <jian.li@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/ddr/imx/imx8m/ddr_init.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/ddr/imx/imx8m/ddr_init.c b/drivers/ddr/imx/imx8m/ddr_init.c
index ba5ae05035..06b4341b11 100644
--- a/drivers/ddr/imx/imx8m/ddr_init.c
+++ b/drivers/ddr/imx/imx8m/ddr_init.c
@@ -162,7 +162,7 @@  int ddr_init(struct dram_timing_info *dram_timing)
 	/* Step26: Set back register in Step4 to the original values if desired */
 	reg32_write(DDRC_RFSHCTL3(0), 0x0000000);
 	/* enable selfref_en by default */
-	setbits_le32(DDRC_PWRCTL(0), 0x1 << 3);
+	setbits_le32(DDRC_PWRCTL(0), 0x1);
 
 	/* enable port 0 */
 	reg32_write(DDRC_PCTRL_0(0), 0x00000001);