diff mbox series

[v7,15/22] riscv: sifive: dts: fu540: Add clock for cpus node

Message ID 20200502100628.24809-16-pragnesh.patel@sifive.com
State Superseded
Delegated to: Andes
Headers show
Series RISC-V SiFive FU540 support SPL | expand

Commit Message

Pragnesh Patel May 2, 2020, 10:06 a.m. UTC 
Add clock-frequency and clocks in cpus node, so that
clock will be enabled by cpu driver.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
---
 arch/riscv/dts/fu540-c000-u-boot.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

Comments

Bin Meng May 2, 2020, 12:43 p.m. UTC | #1 
On Sat, May 2, 2020 at 6:08 PM Pragnesh Patel <pragnesh.patel@sifive.com> wrote:
>
> Add clock-frequency and clocks in cpus node, so that
> clock will be enabled by cpu driver.
>
> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
> ---
>  arch/riscv/dts/fu540-c000-u-boot.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Jagan Teki May 2, 2020, 4:50 p.m. UTC | #2 
On Sat, May 2, 2020 at 3:38 PM Pragnesh Patel <pragnesh.patel@sifive.com> wrote:
>
> Add clock-frequency and clocks in cpus node, so that
> clock will be enabled by cpu driver.
>
> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
> ---

Squash this with 05/22
Pragnesh Patel May 3, 2020, 8:55 a.m. UTC | #3 
Hi Jagan,

>-----Original Message-----
>From: Jagan Teki <jagan@amarulasolutions.com>
>Sent: 02 May 2020 22:20
>To: Pragnesh Patel <pragnesh.patel@sifive.com>
>Cc: U-Boot-Denx <u-boot@lists.denx.de>; Atish Patra
><atish.patra@wdc.com>; Palmer Dabbelt <palmerdabbelt@google.com>; Bin
>Meng <bmeng.cn@gmail.com>; Paul Walmsley <paul.walmsley@sifive.com>;
>Troy Benjegerdes <troy.benjegerdes@sifive.com>; Anup Patel
><anup.patel@wdc.com>; Sagar Kadam <sagar.kadam@sifive.com>; Rick Chen
><rick@andestech.com>
>Subject: Re: [PATCH v7 15/22] riscv: sifive: dts: fu540: Add clock for cpus node
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>On Sat, May 2, 2020 at 3:38 PM Pragnesh Patel <pragnesh.patel@sifive.com>
>wrote:
>>
>> Add clock-frequency and clocks in cpus node, so that clock will be
>> enabled by cpu driver.
>>
>> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
>> ---
>
>Squash this with 05/22

Will update in v8.
diff mbox series

Patch

diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi
index e93b8a9bcf..ab697ab93c 100644
--- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -7,6 +7,8 @@ 
 	cpus {
 		u-boot,dm-spl;
 		cpu0: cpu@0 {
+			clocks = <&prci PRCI_CLK_COREPLL>;
+			clock-frequency = <1000000000>;
 			u-boot,dm-spl;
 			status = "okay";
 			cpu0_intc: interrupt-controller {
@@ -14,24 +16,32 @@ 
 			};
 		};
 		cpu1: cpu@1 {
+			clocks = <&prci PRCI_CLK_COREPLL>;
+			clock-frequency = <1000000000>;
 			u-boot,dm-spl;
 			cpu1_intc: interrupt-controller {
 				u-boot,dm-spl;
 			};
 		};
 		cpu2: cpu@2 {
+			clocks = <&prci PRCI_CLK_COREPLL>;
+			clock-frequency = <1000000000>;
 			u-boot,dm-spl;
 			cpu2_intc: interrupt-controller {
 				 u-boot,dm-spl;
 			};
 		};
 		cpu3: cpu@3 {
+			clocks = <&prci PRCI_CLK_COREPLL>;
+			clock-frequency = <1000000000>;
 			u-boot,dm-spl;
 			cpu3_intc: interrupt-controller {
 				u-boot,dm-spl;
 			};
 		};
 		cpu4: cpu@4 {
+			clocks = <&prci PRCI_CLK_COREPLL>;
+			clock-frequency = <1000000000>;
 			u-boot,dm-spl;
 			cpu4_intc: interrupt-controller {
 				u-boot,dm-spl;