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Fri, 24 Apr 2020 16:52:00 +0000 (GMT) From: Sylwester Nawrocki To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com Cc: sjg@chromium.org, nsaenzjulienne@suse.de, jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com, Sylwester Nawrocki Subject: [PATCH v1 03/10] pci: Move some PCIe register offset definitions to a common header Date: Fri, 24 Apr 2020 18:50:05 +0200 Message-Id: <20200424165012.31915-4-s.nawrocki@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200424165012.31915-1-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprCKsWRmVeSWpSXmKPExsWy7djP87qGkovjDD6eFbDYOGM9q8XUnniL G7/aWC3WHrnLbvGmrZHRYsHkJ6wW22YtZ7M4/Kad1eLblm2MFm/3drI7cHnMbrjI4jFv1gkW j52z7rJ7nL2zg9Gjb8sqRo/1W66yeGw+XR3AHsVlk5Kak1mWWqRvl8CV8WHSXLaCPRIVHz7F NzDOFOli5OSQEDCReP90MlMXIxeHkMAKRokJt+6yQThfGCX2P3/JCuF8ZpQ4/babGablZ9ci qMRyRokPDb3scC2vvuxgAaliEzCU6D3axwhiiwgESFz7OY0RpIhZYCWjxLe+c2AJYYE4iRvv JoKNZRFQlfg/8w1QnIODV8Ba4v9bGYht8hKrNxwAK+EUsJFoPPuKBWSOhMBkdokj144xQRS5 SGxo/MgCYQtLvDq+hR3ClpH4v3M+E0RDM6NEz+7b7BDOBEaJ+8cXMEJUWUvcOfeLDWQzs4Cm xPpd+hBhR4nPz+cygYQlBPgkbrwVBAkzA5mTtk1nhgjzSnS0CUFUq0j8XjUd6hwpie4n/6HO 8ZDYues6IySA+hkl3m68yDiBUX4WwrIFjIyrGMVTS4tz01OLjfNSy/WKE3OLS/PS9ZLzczcx AtPK6X/Hv+5g3Pcn6RCjAAejEg9vxJFFcUKsiWXFlbmHGCU4mJVEeGNKgEK8KYmVValF+fFF pTmpxYcYpTlYlMR5jRe9jBUSSE8sSc1OTS1ILYLJMnFwSjUwcu+8HvfgdsfuE34K0WeOVUf2 vHQR+D1pYW5mwUlr6bMRZg41j7jtYn7kCPlddtR3e6TB4J21X2mSmqcDzyZWScM7P24Z82oc XfJI5/66tJ+bNAMaDU3frl57YpLGdGPjWYE+EQ9ZxEyY7fc9m8dot0Zt0vZvaW8/d1946Cyq pm4X/fPje+YgJZbijERDLeai4kQA6iiVEScDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrMLMWRmVeSWpSXmKPExsVy+t/xe7oGkovjDGae0LTYOGM9q8XUnniL G7/aWC3WHrnLbvGmrZHRYsHkJ6wW22YtZ7M4/Kad1eLblm2MFm/3drI7cHnMbrjI4jFv1gkW j52z7rJ7nL2zg9Gjb8sqRo/1W66yeGw+XR3AHqVnU5RfWpKqkJFfXGKrFG1oYaRnaGmhZ2Ri qWdobB5rZWSqpG9nk5Kak1mWWqRvl6CX8WHSXLaCPRIVHz7FNzDOFOli5OSQEDCR+Nm1iLWL kYtDSGApo0Tzry9sXYwcQAkpifktShA1whJ/rnWxQdR8YpTYsauNESTBJmAo0Xu0D8wWEQiR eHH0ChNIEbPAekaJDTdmsoEkhAViJF6um8QCYrMIqEr8n/mGEWQBr4C1xP+3MhAL5CVWbzjA DGJzCthINJ59BVYuBFSybeZzlgmMfAsYGVYxiqSWFuem5xYb6RUn5haX5qXrJefnbmIEBvi2 Yz+37GDsehd8iFGAg1GJhzfiyKI4IdbEsuLK3EOMEhzMSiK8MSVAId6UxMqq1KL8+KLSnNTi Q4ymQDdNZJYSTc4HRl9eSbyhqaG5haWhubG5sZmFkjhvh8DBGCGB9MSS1OzU1ILUIpg+Jg5O qQbGbUkMBpWX85u+pCi++3r//rYAnZmrm/f93vNpNZu077b0tfxP9Sfp39v3IzVHUjFOfVPM h1ualrLyEdc5tkbnHirTdZDKEmkzX/FaL3Stz4eYBN1Loe0bVUvt9bcwzn0a8Ny0vubHXTMG V6/btwJtsy7dbJ7oxii8eyLfBcV5C0W8Mlz3HXVQYinOSDTUYi4qTgQAyUXvoYYCAAA= X-CMS-MailID: 20200424165200eucas1p20975344302a9a3086cf38738f32d287f X-Msg-Generator: CA X-RootMTR: 20200424165200eucas1p20975344302a9a3086cf38738f32d287f X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200424165200eucas1p20975344302a9a3086cf38738f32d287f References: <20200424165012.31915-1-s.nawrocki@samsung.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Reviewed-by: Bin Meng Signed-off-by: Sylwester Nawrocki Reviewed-by: Nicolas Saenz Julienne --- Changes since RFC: - whitespace clean up. --- drivers/pci/pci-rcar-gen3.c | 8 -------- drivers/pci/pcie_intel_fpga.c | 3 --- include/pci.h | 13 +++++++++++-- 3 files changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c index 30eff67..393f1c9 100644 --- a/drivers/pci/pci-rcar-gen3.c +++ b/drivers/pci/pci-rcar-gen3.c @@ -117,14 +117,6 @@ #define RCAR_PCI_MAX_RESOURCES 4 #define MAX_NR_INBOUND_MAPS 6 -#define PCI_EXP_FLAGS 2 /* Capabilities register */ -#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ -#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ -#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ -#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ -#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ -#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ - enum { RCAR_PCI_ACCESS_READ, RCAR_PCI_ACCESS_WRITE, diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c index 6a9f29c..69363a0 100644 --- a/drivers/pci/pcie_intel_fpga.c +++ b/drivers/pci/pcie_intel_fpga.c @@ -65,9 +65,6 @@ #define IS_ROOT_PORT(pcie, bdf) \ ((PCI_BUS(bdf) == pcie->first_busno) ? true : false) -#define PCI_EXP_LNKSTA 18 /* Link Status */ -#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ - /** * struct intel_fpga_pcie - Intel FPGA PCIe controller state * @bus: Pointer to the PCI bus diff --git a/include/pci.h b/include/pci.h index 174ddd4..5bf91a4 100644 --- a/include/pci.h +++ b/include/pci.h @@ -471,10 +471,19 @@ #define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */ /* PCI Express capabilities */ +#define PCI_EXP_FLAGS 2 /* Capabilities register */ +#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ +#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ #define PCI_EXP_DEVCAP 4 /* Device capabilities */ -#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ +#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ #define PCI_EXP_DEVCTL 8 /* Device Control */ -#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ +#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ +#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ +#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ +#define PCI_EXP_LNKSTA 18 /* Link Status */ +#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ +#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ +#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ /* Include the ID list */