From patchwork Sun Apr 19 15:48:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 1272954 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=nic.cz Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=nic.cz header.i=@nic.cz header.a=rsa-sha256 header.s=default header.b=PtAxbGZP; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 494vT13qmQz9s71 for ; Mon, 20 Apr 2020 01:51:33 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 18B0E81A66; Sun, 19 Apr 2020 17:50:51 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=nic.cz Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; secure) header.d=nic.cz header.i=@nic.cz header.b="PtAxbGZP"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 4BE3480574; Sun, 19 Apr 2020 17:49:25 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from mail.nic.cz (lists.nic.cz [217.31.204.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id B90CA81A08 for ; Sun, 19 Apr 2020 17:48:56 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=nic.cz Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=marek.behun@nic.cz Received: from dellmb.labs.office.nic.cz (unknown [IPv6:2001:1488:fffe:6:cac7:3539:7f1f:463]) by mail.nic.cz (Postfix) with ESMTP id 5D95E140EAA; Sun, 19 Apr 2020 17:48:56 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=nic.cz; s=default; t=1587311336; bh=5MCm1NW70Fk2yj0J3jmJ4se18NCYb2wU49McQ60Rf24=; h=From:To:Date; b=PtAxbGZPy7800qiKgtfen1T4GtvVoZN0DfZp+4Yvc0f29dwOjpj+XrEL2Nw1fT0L/ N+4iW0b02WaDccpI9LSMLqjMhS7eECHgu53NODvePKjIeTn1WyKfkRj4FK3YW3P6+S eIgxIeV7y6Ex1Sv1lpbzaJ2NyyilbAIFyovpq21I= From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Stefan Roese Cc: u-boot@lists.denx.de, Konstantin Porotchkin , make@marvell.com, Vladimir Vid , "Matwey V . Kornilov" , Miquel Raynal , Gregory CLEMENT , Andrew Lunn , Thomas Petazzoni , Tomasz Maciej Nowak , Ellie Reeves , Vladimir Oltean , Marek Vasut , =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH u-boot-marvell 07/11] pci: aardvark: add PHY support Date: Sun, 19 Apr 2020 17:48:46 +0200 Message-Id: <20200419154850.25868-8-marek.behun@nic.cz> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200419154850.25868-1-marek.behun@nic.cz> References: <20200419154850.25868-1-marek.behun@nic.cz> MIME-Version: 1.0 X-Spamd-Bar: / X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean Use generic-phy API to power on PCIe PHY. Since the new comphy drivers only does a SMC call into ARM Trusted Firmware and the comphy driver in ATF does not do TX Enabling (step 7 in PCIe PHY power on algorithm), add TX enabling into this driver. Signed-off-by: Marek Behún --- drivers/pci/pci-aardvark.c | 55 +++++++++++++++++++++++++++++++++++++- 1 file changed, 54 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index d678e0b599..99398e7a7e 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -30,6 +30,7 @@ #include #include #include +#include #include /* PCIe core registers */ @@ -92,6 +93,8 @@ #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4) #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5) #define PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE BIT(6) +#define PCIE_CORE_REF_CLK_REG (CONTROL_BASE_ADDR + 0x14) +#define PCIE_CORE_REF_CLK_TX_ENABLE BIT(1) /* LMI registers base address and register offsets */ #define LMI_BASE_ADDR 0x6000 @@ -141,11 +144,13 @@ * number which may vary depending on the PCIe setup * (PEX switches etc). * @device: The pointer to PCI uclass device. + * @phy: The PCIe generic-phy instance. */ struct pcie_advk { void *base; int first_busno; struct udevice *dev; + struct phy phy; }; static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg) @@ -512,6 +517,11 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie) { u32 reg; + /* Enable TX */ + reg = advk_readl(pcie, PCIE_CORE_REF_CLK_REG); + reg |= PCIE_CORE_REF_CLK_TX_ENABLE; + advk_writel(pcie, reg, PCIE_CORE_REF_CLK_REG); + /* Set to Direct mode */ reg = advk_readl(pcie, CTRL_CONFIG_REG); reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT); @@ -597,6 +607,47 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie) return 0; } +/** + * pcie_advk_phy_power_on() - Initialize generic-phy for this controller + */ +static int pcie_advk_phy_power_on(struct pcie_advk *pcie) +{ + struct udevice *dev = pcie->dev; + struct phy *phy = &pcie->phy; + int ret; + + ret = generic_phy_get_by_index(dev, 0, phy); + if (ret && ret != -ENOENT) { + dev_err(dev, "failed to get PCIe generic-phy\n"); + return ret; + } + + ret = generic_phy_init(phy); + if (ret) { + dev_err(dev, "failed to init PCIe generic-phy\n"); + return ret; + } + + ret = generic_phy_set_mode(phy, PHY_MODE_PCIE, 0); + if (ret) { + dev_err(dev, "failed to set mode on PCIe generic-phy\n"); + goto err; + } + + ret = generic_phy_power_on(phy); + if (ret) { + dev_err(dev, "failed to power on PCIe generic-phy\n"); + goto err; + } + + return 0; + +err: + generic_phy_exit(phy); + + return ret; +} + /** * pcie_advk_probe() - Probe the PCIe bus for active link * @@ -611,6 +662,9 @@ static int pcie_advk_probe(struct udevice *dev) { struct pcie_advk *pcie = dev_get_priv(dev); + pcie->dev = pci_get_controller(dev); + pcie_advk_phy_power_on(pcie); + #if CONFIG_IS_ENABLED(DM_GPIO) struct gpio_desc reset_gpio; @@ -640,7 +694,6 @@ static int pcie_advk_probe(struct udevice *dev) #endif /* DM_GPIO */ pcie->first_busno = dev->seq; - pcie->dev = pci_get_controller(dev); return pcie_advk_setup_hw(pcie); }