From patchwork Sat Mar 14 00:11:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 1254740 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=RLSerqnu; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48fNLJ5tFhz9sPJ for ; Sat, 14 Mar 2020 11:12:40 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 3D5B981656; Sat, 14 Mar 2020 01:12:10 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.b="RLSerqnu"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 2D4B4813CC; Sat, 14 Mar 2020 01:11:51 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from esa6.hgst.iphmx.com (esa6.hgst.iphmx.com [216.71.154.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 62A57813C3 for ; Sat, 14 Mar 2020 01:11:41 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=wdc.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=prvs=33551ae11=atish.patra@wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1584144702; x=1615680702; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1rXXfh52CYjKiIbOqTUM+ZdwSfu9H3xMM+jNKvi821g=; b=RLSerqnuszzRZKsDIYHH6ssxni3OvoV75dMoAaVzTmFqDZKyTu5oTd9J a2hlwvjEdK/WRHS4sz+Dnm1YT+4QRUcjvqj5obqfATNjdUXXQOwaIyGl5 XTCxNNTClx7qijm75rcGRdu6biBTdyY5dk6k0SNxgyegr7Ng1KpNi3QDk FN2sLFdqme70hjXix6LsfNW1rDv3RrWkE8H1V+db2yOyMdw7qolEOkqvz R5pTGrWSxCEa6GmIQuE9CnL64Slf9KNxk406zE4OPa5Ga/h0LKC2tbHbK ENIjfpKjHcjSKuq+j6MUml3r8s/MsWqVOIIMwTtyXflDT7iUtnCCvIEqF w==; IronPort-SDR: t/mKvOiBPbV/4N40tNgfbYhrSecfh6eLR2unRaqCbfP5mOMXEyoSy6CY2AiYHLMlajUGmdKf1y Q9hjmutiEHQSlnzfGLnPp3W5YsmDyidjEhWyr0vgo8dg4s+BRdbDNamsrtjX7urzaK103MhWxh bzI73OcZhtwbh4gFg1I8ClayED8BMOKSJ0z1o/sDt1ec6NwSddgqQ9mOzc/XABZvPDkprqUzGe jvQ8qIrH/KUiX/8jTd0zBLeN4jh6FgGcEHJiLdob4Y3J4EmXUh1Mteb65QLFYSxNlBrezCjzmJ iS8= X-IronPort-AV: E=Sophos;i="5.70,550,1574092800"; d="scan'208";a="133903980" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 14 Mar 2020 08:11:38 +0800 IronPort-SDR: HOuAq8IdXIgLoXciCtDWiZud/i9xKqPwGpJaWrnpfQQE3wT4dln+UwDMonSoNXqu2JEZau8WuC Avz1tQyGBhn0GHMmz19DYGSoI1eaWSDB01v7Vi2W+MdEwURSLUZsKYycv9GUhOzsDP6JImP668 tA6XmlLEVvl8B02Lmk2WEZujq4l95iCdsnBY1JajF1/B4u7q0UuhfjaWfkTrUlcL6xWTaJzsFG G5VpgBH++TKNuiQ/2EC/C2UVMv42lMuN1zNolWtj46M5pm6kzpESFyqQeFXaJqdO0Y4Kd7J4fU i7QrnDGCZfU39ciPaMICT62z Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Mar 2020 17:03:12 -0700 IronPort-SDR: 7Vi3MipliGNUNRTDqmSS78fsVxLQ0SVH5J4f+BQMCNsEdyvoM1kS9LW9igAo06VDuzpBDpI1YF 4koL2vby5x/MlXID8sFp/g1B6nH3fDv7ffSgoEzLGvTDouUKvjfgLc7/VJ2ME7BFXaCvGkGkpJ TDRrIPY9b17Qqkv8xI68es8E+18e2DPtJ0WSTYveQsJk7gdSPmfTBOv1LoOe5LLuO+9l9B0qTA 0UsPj5HzBW6OVC722OKSqGbSaNbRtPh4e2pE+EJhiNHJ+s3B4cszg2efji1Fj+cvpkynzpv/1u /uk= WDCIronportException: Internal Received: from wdapacbjl0003.my.asia.wdc.com (HELO yoda.hgst.com) ([10.86.54.92]) by uls-op-cesaip02.wdc.com with ESMTP; 13 Mar 2020 17:11:37 -0700 From: Atish Patra To: u-boot@lists.denx.de Cc: Atish Patra , Alexander Graf , Anup Patel , Bin Meng , Heinrich Schuchardt , Lukas Auer , Palmer Dabbelt , Rick Chen , abner.chang@hpe.com, daniel.schaefer@hpe.com Subject: [PATCH v2 3/4] riscv: Provide a mechanism for riscv boards to parse reserved memory Date: Fri, 13 Mar 2020 17:11:31 -0700 Message-Id: <20200314001132.17393-4-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200314001132.17393-1-atish.patra@wdc.com> References: <20200314001132.17393-1-atish.patra@wdc.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean In RISC-V, M-mode software can reserve physical memory regions by setting appropriate physical memory protection (PMP) csr. As the PMP csr are accessible only in M-mode, S-mode U-Boot can not read this configuration directly. However, M-mode software can pass this information via reserved-memory node in device tree so that S-mode software can access this information. In U-boot, any board may use the DT in following ways. 1. OF_SEPARTE: It ignores the DT from previous stage and uses the DT from U-Boot sources. 2. OF_PRIOR_STATE: It reuses the DT from previous stage. For case 1: U-Boot needs to parse the reserved-memory node from the DT passed from the previous stage and update the DT in use. This patch provides a framework to do that from any RISC-V boards. Signed-off-by: Atish Patra --- arch/riscv/cpu/start.S | 1 + arch/riscv/include/asm/global_data.h | 1 + arch/riscv/include/asm/u-boot-riscv.h | 1 + arch/riscv/lib/asm-offsets.c | 1 + arch/riscv/lib/bootm.c | 37 +++++++++++++++++++++++++++ 5 files changed, 41 insertions(+) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 6b3ff99c3882..0282685c2906 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -121,6 +121,7 @@ call_board_init_f_0: jal board_init_f_init_reserve + SREG s1, GD_FIRMWARE_FDT_ADDR(gp) /* save the boot hart id to global_data */ SREG tp, GD_BOOT_HART(gp) diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index b74bd7e738bb..51ac8d1c98e2 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -15,6 +15,7 @@ /* Architecture-specific global data */ struct arch_global_data { long boot_hart; /* boot hart id */ + phys_addr_t firmware_fdt_addr; #ifdef CONFIG_SIFIVE_CLINT void __iomem *clint; /* clint base address */ #endif diff --git a/arch/riscv/include/asm/u-boot-riscv.h b/arch/riscv/include/asm/u-boot-riscv.h index 49febd588102..b7bea0ba184d 100644 --- a/arch/riscv/include/asm/u-boot-riscv.h +++ b/arch/riscv/include/asm/u-boot-riscv.h @@ -17,5 +17,6 @@ int cleanup_before_linux(void); /* board/.../... */ int board_init(void); void board_quiesce_devices(void); +int riscv_board_reserved_mem_fixup(void *fdt); #endif /* _U_BOOT_RISCV_H_ */ diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c index 4fa4fd371473..7301c1b98e23 100644 --- a/arch/riscv/lib/asm-offsets.c +++ b/arch/riscv/lib/asm-offsets.c @@ -14,6 +14,7 @@ int main(void) { DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart)); + DEFINE(GD_FIRMWARE_FDT_ADDR, offsetof(gd_t, arch.firmware_fdt_addr)); #ifndef CONFIG_XIP DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts)); #endif diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index f927694ae32f..3a4d0bf14c86 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -19,6 +19,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -26,6 +27,42 @@ __weak void board_quiesce_devices(void) { } +int riscv_board_reserved_mem_fixup(void *fdt) +{ + uint32_t phandle; + struct fdt_memory pmp_mem; + int err; + void *src_fdt_addr; + int offset, node; + phys_addr_t addr, size; + + src_fdt_addr = map_sysmem(gd->arch.firmware_fdt_addr, 0); + offset = fdt_path_offset(src_fdt_addr, "/reserved-memory"); + if (offset < 0) { + printf("No reserved memory region found in FDT\n"); + return offset; + } + + fdt_for_each_subnode(node, src_fdt_addr, offset) { + const char *name = fdt_get_name(src_fdt_addr, node, NULL); + + addr = fdtdec_get_addr_size(src_fdt_addr, node, "reg", &size); + if (addr == FDT_ADDR_T_NONE) { + debug("failed to read address/size for %s\n", name); + continue; + } + pmp_mem.start = addr; + pmp_mem.end = addr + size; + err = fdtdec_add_reserved_memory(fdt, name, &pmp_mem, &phandle); + if (err < 0) { + printf("failed to add reserved memory: %d\n", err); + return err; + } + } + + return 0; +} + int arch_fixup_fdt(void *blob) { u32 size;