From patchwork Fri Feb 21 01:25:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ley Foon Tan X-Patchwork-Id: 1241737 X-Patchwork-Delegate: simon.k.r.goldschmidt@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48Nv0V2tgMz9sRG for ; Fri, 21 Feb 2020 12:25:27 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 8CEAA818DA; Fri, 21 Feb 2020 02:25:19 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 0ADC8818E6; Fri, 21 Feb 2020 02:25:18 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: * X-Spam-Status: No, score=1.1 required=5.0 tests=AC_FROM_MANY_DOTS, BAYES_00, SPF_HELO_NONE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.2 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id E23D8818C4 for ; Fri, 21 Feb 2020 02:25:13 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ley.foon.tan@intel.com X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Feb 2020 17:25:11 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,466,1574150400"; d="scan'208";a="435029824" Received: from unknown (HELO lftan) ([10.226.248.145]) by fmsmga005.fm.intel.com with SMTP; 20 Feb 2020 17:25:08 -0800 Received: by lftan (sSMTP sendmail emulation); Fri, 21 Feb 2020 09:25:07 +0800 From: Ley Foon Tan To: u-boot@lists.denx.de Cc: Marek Vasut , Ley Foon Tan , Chin Liang See , Simon Goldschmidt , Tien Fong Chee , Ley Foon Tan Subject: [PATCH 1/2] configs: socfpga: Add QSPI support for Cyclone 5 Date: Fri, 21 Feb 2020 09:25:05 +0800 Message-Id: <20200221012506.5042-1-ley.foon.tan@intel.com> X-Mailer: git-send-email 2.17.1 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean Add QSPI boot support to boot target devices list. Platform can provide their own boot settings through SOCFPGA_BOOT_SETTINGS macro if needed. Add SOCFPGA_BOOT_SETTINGS for Cyclone 5. Signed-off-by: Ley Foon Tan --- include/configs/socfpga_common.h | 18 ++++++++++++++++++ include/configs/socfpga_cyclone5_socdk.h | 18 ++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 8d10469e7c..f3ddfca289 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -228,11 +228,28 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define BOOT_TARGET_DEVICES_MMC(func) #endif +#ifdef CONFIG_CMD_SF +#define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, na) +#else +#define BOOT_TARGET_DEVICES_QSPI(func) +#endif + +#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ + "bootcmd_qspi=run qspiload; run qspiboot\0" + +#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \ + "qspi " + #define BOOT_TARGET_DEVICES(func) \ BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_QSPI(func) \ BOOT_TARGET_DEVICES_PXE(func) \ BOOT_TARGET_DEVICES_DHCP(func) +#ifndef SOCFPGA_BOOT_SETTINGS +#define SOCFPGA_BOOT_SETTINGS +#endif + #include #ifndef CONFIG_EXTRA_ENV_SETTINGS @@ -245,6 +262,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); "pxefile_addr_r=0x02200000\0" \ "ramdisk_addr_r=0x02300000\0" \ "socfpga_legacy_reset_compat=1\0" \ + SOCFPGA_BOOT_SETTINGS \ BOOTENV #endif diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h index 028db2a09e..62ad001c4b 100644 --- a/include/configs/socfpga_cyclone5_socdk.h +++ b/include/configs/socfpga_cyclone5_socdk.h @@ -14,6 +14,24 @@ #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +/* QSPI boot */ +#define FDT_SIZE __stringify(0x00010000) +#define KERNEL_SIZE __stringify(0x005d0000) +#define QSPI_FDT_ADDR __stringify(0x00220000) +#define QSPI_KERNEL_ADDR __stringify(0x00230000) + +#define SOCFPGA_BOOT_SETTINGS \ + "fdt_size=" FDT_SIZE "\0" \ + "kernel_size=" KERNEL_SIZE "\0" \ + "qspi_fdt_addr=" QSPI_FDT_ADDR "\0" \ + "qspi_kernel_addr=" QSPI_KERNEL_ADDR "\0" \ + "qspiboot=setenv bootargs earlycon " \ + "root=/dev/mtdblock1 rw rootfstype=jffs2; " \ + "bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "qspiload=sf probe; " \ + "sf read ${kernel_addr_r} ${qspi_kernel_addr} ${kernel_size}; " \ + "sf read ${fdt_addr_r} ${qspi_fdt_addr} ${fdt_size}\0" + /* The rest of the configuration is shared */ #include