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Sun, 26 Jan 2020 21:08:34 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id h23sm4313195ilf.57.2020.01.26.21.08.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Jan 2020 21:08:33 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Subject: [PATCH 011/108] x86: apl: Add Global NVS table header Date: Sun, 26 Jan 2020 22:05:18 -0700 Message-Id: <20200126220508.11.I4aa2fe09882dcf5a040603469bac136e4342d350@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200127050655.170614-1-sjg@chromium.org> References: <20200127050655.170614-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.26 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.101.4 at phobos.denx.de X-Virus-Status: Clean Add the C version of this header. It includes a few Chrome OS bits which are disabled for a normal build. Signed-off-by: Simon Glass --- .../include/asm/arch-apollolake/global_nvs.h | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 arch/x86/include/asm/arch-apollolake/global_nvs.h diff --git a/arch/x86/include/asm/arch-apollolake/global_nvs.h b/arch/x86/include/asm/arch-apollolake/global_nvs.h new file mode 100644 index 0000000000..0ea6da5cf9 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/global_nvs.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015-2017 Intel Corp. + * (Written by Lance Zhao for Intel Corp.) + * Copyright Google LLC 2019 + * + * Modified from coreboot apollolake/include/soc/nvs.h + */ + +#ifndef _GLOBAL_NVS_H_ +#define _GLOBAL_NVS_H_ + +struct __packed acpi_global_nvs { + /* Miscellaneous */ + u8 pcnt; /* 0x00 - Processor Count */ + u8 ppcm; /* 0x01 - Max PPC State */ + u8 lids; /* 0x02 - LID State */ + u8 pwrs; /* 0x03 - AC Power State */ + u8 dpte; /* 0x04 - Enable DPTF */ + u32 cbmc; /* 0x05 - 0x08 - coreboot Memory Console */ + u64 pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */ + u64 gpei; /* 0x11 - 0x18 - GPE Wake Source */ + u64 nhla; /* 0x19 - 0x20 - NHLT Address */ + u32 nhll; /* 0x21 - 0x24 - NHLT Length */ + u32 prt0; /* 0x25 - 0x28 - PERST_0 Address */ + u8 scdp; /* 0x29 - SD_CD GPIO portid */ + u8 scdo; /* 0x2A - GPIO pad offset relative to the community */ + u8 uior; /* 0x2B - UART debug controller init on S3 resume */ + u8 ecps; /* 0x2C - SGX Enabled status */ + u64 emna; /* 0x2D - 0x34 EPC base address */ + u64 elng; /* 0x35 - 0x3C EPC Length */ + u8 unused[195]; +#ifdef CONFIG_CHROMEOS + /* ChromeOS specific (0x100 - 0xfff) */ + struct chromeos_acpi chromeos; +#else + u8 unused2[0xf00]; +#endif +}; +#ifdef CONFIG_CHROMEOS +check_member(acpi_global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); +#endif + +#endif /* _GLOBAL_NVS_H_ */