diff mbox series

[12/22] ddr: imx8m: Add DRAM PLL to generate 1000Mhz output

Message ID 20191230102802.10899-13-peng.fan@nxp.com
State Accepted
Commit 4a41a1a6f06ed86feae9f52d2e8ece5cce0a850d
Delegated to: Stefano Babic
Headers show
Series imx: add i.MX8MP support | expand

Commit Message

Peng Fan Dec. 30, 2019, 10:09 a.m. UTC 
We will generate DRAM 4000MT/s as default for i.MX8MP.
So need DRAM PLL to generate 1000Mhz clock to DDR PHY and controller.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/ddr/imx/imx8m/ddrphy_utils.c | 4 ++++
 1 file changed, 4 insertions(+)
diff mbox series

Patch

diff --git a/drivers/ddr/imx/imx8m/ddrphy_utils.c b/drivers/ddr/imx/imx8m/ddrphy_utils.c
index e60503309e..7b4ab7c77a 100644
--- a/drivers/ddr/imx/imx8m/ddrphy_utils.c
+++ b/drivers/ddr/imx/imx8m/ddrphy_utils.c
@@ -106,6 +106,10 @@  void wait_ddrphy_training_complete(void)
 void ddrphy_init_set_dfi_clk(unsigned int drate)
 {
 	switch (drate) {
+	case 4000:
+		dram_pll_init(MHZ(1000));
+		dram_disable_bypass();
+		break;
 	case 3200:
 		dram_pll_init(MHZ(800));
 		dram_disable_bypass();