diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3dc9c4d41c..cc39129556 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -568,6 +568,9 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
 	vf610-pcm052.dtb \
 	vf610-bk4r1.dtb
 
+dtb-$(CONFIG_MX28) += \
+	imx28-xea.dtb
+
 dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \
 	imx53-kp.dtb \
 	imx53-m53menlo.dtb
diff --git a/arch/arm/dts/imx28-xea-u-boot.dtsi b/arch/arm/dts/imx28-xea-u-boot.dtsi
new file mode 100644
index 0000000000..cc2ced5d2d
--- /dev/null
+++ b/arch/arm/dts/imx28-xea-u-boot.dtsi
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier:     GPL-2.0+ or X11
+ */
+
+/*
+ * The minimal augmentation DTS U-Boot file to allow eMMC driver
+ * configuration in SPL for falcon boot.
+ */
+#include "imx28-u-boot.dtsi"
+/ {
+	apb@80000000 {
+		u-boot,dm-spl;
+
+		apbh@80000000 {
+			u-boot,dm-spl;
+		};
+
+		apbx@80040000 {
+			u-boot,dm-spl;
+		};
+	};
+};
+
+&clks {
+	u-boot,dm-spl;
+};
+
+&gpio0 {
+	u-boot,dm-spl;
+};
+
+&pinctrl {
+	u-boot,dm-spl;
+};
+
+&ssp0 {
+	u-boot,dm-spl;
+};
+
+&ssp3 {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx28-xea.dts b/arch/arm/dts/imx28-xea.dts
new file mode 100644
index 0000000000..5de6774c5a
--- /dev/null
+++ b/arch/arm/dts/imx28-xea.dts
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier:     GPL-2.0+ or X11
+ *
+ */
+
+/dts-v1/;
+
+#include "imx28.dtsi"
+
+/ {
+	model = "Liebherr (LWE) XEA i.MX28 Board";
+	compatible = "lwe,xea", "fsl,imx28";
+
+	aliases {
+		spi3 = &ssp3;
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x40000000 0x10000000>;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "3P3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	reg_fec_3v3: regulator-fec-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "fec-3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&mac0 {
+	phy-mode = "rmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&mac0_pins_a>;
+	phy-supply = <&reg_fec_3v3>;
+	phy-reset-gpios = <&gpio2 13 GPIO_ACTIVE_LOW>;
+	phy-reset-duration = <1>;
+	phy-reset-post-delay = <1>;
+	status = "okay";
+
+	fixed-link {
+	      speed = <100>;
+	      full-duplex;
+	};
+};
+
+&ssp0 {
+	compatible = "fsl,imx28-mmc";
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_8bit_pins_a>;
+	bus-width = <8>;
+	vmmc-supply = <&reg_3p3v>;
+	non-removable;
+	status = "okay";
+};
+
+&ssp3 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "fsl,imx28-spi";
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi3_pins_b>;
+	status = "okay";
+	spi-max-frequency = <40000000>;
+	num-cs = <2>;
+
+	flash0: s25fl256s@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <40000000>;
+		reg = <0>;
+
+		partition@0 {
+			label = "SPL (spi)";
+			reg = <0x0 0x10000>;
+			read-only;
+		};
+		partition@1 {
+			label = "u-boot (spi)";
+			reg = <0x10000 0x70000>;
+			read-only;
+		};
+		partition@2 {
+			label = "uboot-env (spi)";
+			reg = <0x80000 0x20000>;
+		};
+		partition@3 {
+			label = "kernel (spi)";
+			reg = <0x100000 0x400000>;
+		};
+		partition@4 {
+			label = "swupdate (spi)";
+			reg = <0x50000 0x800000>;
+		};
+	};
+};
diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig
index 68072d5a1f..b90d7b6e41 100644
--- a/arch/arm/mach-imx/mxs/Kconfig
+++ b/arch/arm/mach-imx/mxs/Kconfig
@@ -60,6 +60,9 @@ config TARGET_SC_SPS_1
 config TARGET_TS4600
 	bool "Support TS4600"
 
+config TARGET_XEA
+	bool "Support XEA"
+
 endchoice
 
 config SYS_SOC
@@ -67,6 +70,7 @@ config SYS_SOC
 
 source "board/bluegiga/apx4devkit/Kconfig"
 source "board/freescale/mx28evk/Kconfig"
+source "board/liebherr/xea/Kconfig"
 source "board/ppcag/bg0900/Kconfig"
 source "board/schulercontrol/sc_sps_1/Kconfig"
 source "board/technologic/ts4600/Kconfig"
diff --git a/board/liebherr/xea/Kconfig b/board/liebherr/xea/Kconfig
new file mode 100644
index 0000000000..5428de4646
--- /dev/null
+++ b/board/liebherr/xea/Kconfig
@@ -0,0 +1,24 @@
+if TARGET_XEA
+
+config SYS_BOARD
+	default "xea"
+
+config SYS_VENDOR
+	default "liebherr"
+
+config SYS_SOC
+	default "mxs"
+
+config SYS_CONFIG_NAME
+	default "xea"
+
+config ENV_SIZE
+	default 0x2000
+
+config ENV_SECT_SIZE
+	default 0x10000 if ENV_IS_IN_SPI_FLASH
+
+config ENV_OFFSET
+	default 0x80000 if ENV_IS_IN_SPI_FLASH
+
+endif
diff --git a/board/liebherr/xea/MAINTAINERS b/board/liebherr/xea/MAINTAINERS
new file mode 100644
index 0000000000..623184d0f8
--- /dev/null
+++ b/board/liebherr/xea/MAINTAINERS
@@ -0,0 +1,6 @@
+XEA BOARD
+M:	Lukasz Majewski <lukma@denx.de>
+S:	Maintained
+F:	board/liebherr/xea/
+F:	include/configs/xea.h
+F:	configs/imx28_xea_defconfig
diff --git a/board/liebherr/xea/Makefile b/board/liebherr/xea/Makefile
new file mode 100644
index 0000000000..abf500857f
--- /dev/null
+++ b/board/liebherr/xea/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2019
+# Lukasz Majewski, DENX Software Engineering, lukma@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= xea.o
+
+ifdef	CONFIG_SPL_BUILD
+obj-y	+= spl_xea.o
+endif
diff --git a/board/liebherr/xea/README b/board/liebherr/xea/README
new file mode 100644
index 0000000000..3e55d3ea43
--- /dev/null
+++ b/board/liebherr/xea/README
@@ -0,0 +1,63 @@
+Building SPL/U-Boot for xea board
+=================================
+
+Setup environment, configure and build, e.g. by:
+
+ $ make imx28_xea_defconfig
+ $ make -j4 u-boot.sb u-boot.img
+
+Now you should see u-boot.sb and u-boot.img files in the build directory.
+
+
+Booting
+=======
+
+The boot ROM loads SPL from SPI NOR flash into SRAM.  SPL configures
+DRAM and loads either a Linux kernel (falcon mode) or, if the rescue
+pin is asserted, the main U-Boot.  Both kernel and U-Boot reside in
+eMMC boot partition 0.  For redundancy, a copy of U-Boot is also
+stored in SPI flash.  If a valid kernel image is not found, U-Boot is
+loaded from eMMC or, if this fails, SPI flash.
+
+Boot area layout
+----------------
+
+SPI NOR
+Offset          Function        File
+------------------------------------------
+0x00000000      SPL             u-boot.sb
+0x00010000      U-Boot          u-boot.img
+0x00080000      Environment
+
+eMMC
+Offset          Function        File
+------------------------------------------
+0x00000000      U-Boot          u-boot.img
+0x00080000      Devicetree      imx28-bttc.dtb
+0x00100000      Kernel          uImage
+
+
+Falcon mode
+===========
+
+In falcon mode, the default, SPL loads the kernel and devicetree
+directly.  For this to work, the stored devicetree must include
+correct "memory" and "chosen" nodes as these are not updated by SPL
+before booting the kernel.
+
+
+Updating from U-Boot
+====================
+
+The default U-Boot environment includes command sequences to update
+SPL, U-Boot, and kernel over TFTP.  These are as follows:
+
+- update_spl: writes u-boot.sb to SPI NOR
+- update_uboot: writes u-boot.img to eMMC and SPI NOR
+- update_kernel: writes kernel and devicetree to eMMC
+
+They can be invoked at the U-Boot prompt using the "run" command,
+e.g. "run update_spl" to update the SPL.
+
+These update commands download the above-named files from the
+${hostname} directory on the server provided by DHCP.
diff --git a/board/liebherr/xea/spl_xea.c b/board/liebherr/xea/spl_xea.c
new file mode 100644
index 0000000000..d88b75bb3a
--- /dev/null
+++ b/board/liebherr/xea/spl_xea.c
@@ -0,0 +1,303 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * DENX M28 Boot setup
+ *
+ * Copyright (C) 2019 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * Copyright (C) 2018 DENX Software Engineering
+ * Måns Rullgård, DENX Software Engineering, mans@mansr.com
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define	MUX_CONFIG_LCD	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+#define	MUX_CONFIG_BOOT	(MXS_PAD_3V3 | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_TSC	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_SSP0	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_SSP2	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_ENET	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_NOPULL)
+#define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
+
+const iomux_cfg_t iomux_setup[] = {
+	/* AUART0 IRDA */
+	MX28_PAD_AUART0_RX__AUART0_RX,
+	MX28_PAD_AUART0_TX__AUART0_TX,
+
+	/* AUART 4 RS422 */
+	MX28_PAD_AUART0_CTS__AUART4_RX,
+	MX28_PAD_AUART0_RTS__AUART4_TX,
+
+	/* USB0 */
+	MX28_PAD_AUART1_CTS__USB0_OVERCURRENT,
+	MX28_PAD_AUART1_RTS__USB0_ID,
+	MX28_PAD_LCD_VSYNC__GPIO_1_28, /* PRW_On */
+
+	/* USB1 */
+	MX28_PAD_PWM2__USB1_OVERCURRENT,
+
+	/* eMMC */
+	MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DETECT__GPIO_2_9, /* Reset for eMMC */
+	MX28_PAD_SSP0_SCK__SSP0_SCK | MUX_CONFIG_SSP0,
+
+	/* DIG Keys */
+	MX28_PAD_GPMI_D00__GPIO_0_0,
+	MX28_PAD_GPMI_D01__GPIO_0_1,
+	MX28_PAD_GPMI_D02__GPIO_0_2,
+	MX28_PAD_GPMI_D03__GPIO_0_3,
+	MX28_PAD_GPMI_D04__GPIO_0_4,
+	MX28_PAD_GPMI_D05__GPIO_0_5,
+	MX28_PAD_GPMI_D06__GPIO_0_6,
+	MX28_PAD_GPMI_D07__GPIO_0_7,
+
+	/* ADR_0-2 */
+	MX28_PAD_GPMI_CE1N__GPIO_0_17,
+	MX28_PAD_GPMI_CE2N__GPIO_0_18,
+	MX28_PAD_GPMI_CE3N__GPIO_0_19,
+
+	/* Read Keys */
+	MX28_PAD_GPMI_RDY0__GPIO_0_20,
+
+	/* LATCH_EN */
+	MX28_PAD_GPMI_RDY1__GPIO_0_21,
+
+	/* Power off */
+	MX28_PAD_GPMI_RDN__GPIO_0_24,
+
+	/* I2C1 Touch */
+	MX28_PAD_AUART2_CTS__GPIO_3_10,
+	MX28_PAD_AUART2_RTS__GPIO_3_11,
+	MX28_PAD_GPMI_RDY2__GPIO_0_22, /* Touch Reset */
+
+	/* TIVA */
+	MX28_PAD_AUART1_RX__SSP2_CARD_DETECT,
+	MX28_PAD_SSP2_MISO__SSP2_D0,
+	MX28_PAD_SSP2_MOSI__SSP2_CMD,
+	MX28_PAD_SSP2_SCK__SSP2_SCK,
+	MX28_PAD_SSP2_SS0__SSP2_D3,
+	MX28_PAD_SSP2_SS1__GPIO_2_20,
+	MX28_PAD_SSP2_SS2__GPIO_2_21,
+
+	/* SPI3 NOR-Flash */
+	MX28_PAD_AUART1_TX__SSP3_CARD_DETECT,
+	MX28_PAD_AUART2_RX__SSP3_D1,
+	MX28_PAD_AUART2_TX__SSP3_D2,
+	MX28_PAD_SSP3_MISO__SSP3_D0,
+	MX28_PAD_SSP3_MOSI__SSP3_CMD,
+	MX28_PAD_SSP3_SCK__SSP3_SCK,
+	MX28_PAD_SSP3_SS0__SSP3_D3,
+
+	/* NOR-Flash CMD */
+	MX28_PAD_LCD_RS__GPIO_1_26, /* Hold */
+	MX28_PAD_LCD_WR_RWN__GPIO_1_25, /* write protect */
+
+	/* I2C0 Codec */
+	MX28_PAD_I2C0_SCL__I2C0_SCL,
+	MX28_PAD_I2C0_SDA__I2C0_SDA,
+
+	/* I2S Codec */
+	MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK,
+	MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK,
+	MX28_PAD_SAIF0_MCLK__SAIF0_MCLK,
+	MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0,
+	MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0,
+
+	/* PWR-Hold */
+	MX28_PAD_SPDIF__GPIO_3_27,
+
+	/* EMI */
+	MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
+
+	MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+
+	/* Uart3 Bluetooth-Interface */
+	MX28_PAD_AUART3_CTS__AUART3_CTS,
+	MX28_PAD_AUART3_RTS__AUART3_RTS,
+	MX28_PAD_AUART3_RX__AUART3_RX,
+	MX28_PAD_AUART3_TX__AUART3_TX,
+
+	/* framebuffer */
+	MX28_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD,
+
+	/* DUART RS232 */
+	MX28_PAD_PWM0__DUART_RX,
+	MX28_PAD_PWM1__DUART_TX,
+
+	/* FEC Ethernet */
+	MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RX_CLK__GPIO_4_13, /* Phy Interrupt */
+	MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TX_CLK__GPIO_4_5, /* n.c. */
+	MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
+	MX28_PAD_SSP1_CMD__GPIO_2_13, /* PHY reset */
+
+	/* TIVA boot control */
+	MX28_PAD_GPMI_RDY3__GPIO_0_23 | MUX_CONFIG_BOOT, /* TIVA0 */
+	MX28_PAD_GPMI_WRN__GPIO_0_25 | MUX_CONFIG_BOOT, /* TIVA1 */
+};
+
+u32 mxs_dram_vals[] = {
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000100, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00010101, 0x01010101,
+	0x000f0f01, 0x0f02010a, 0x00000000, 0x00010101,
+	0x00000100, 0x00000100, 0x00000000, 0x00000002,
+	0x01010000, 0x07080403, 0x07005303, 0x0b0000c8,
+	0x0200a0c1, 0x0002040c, 0x0038430a, 0x04290322,
+	0x02040203, 0x00c8002b, 0x00000000, 0x00000000,
+	0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
+	0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
+	0x00000003, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000612, 0x01000102,
+	0x06120612, 0x00000200, 0x00020007, 0xf4004a27,
+	0xf4004a27, 0xf4004a27, 0xf4004a27, 0x07400300,
+	0x07400300, 0x07400300, 0x07400300, 0x00000005,
+	0x00000000, 0x00000000, 0x01000000, 0x00000000,
+	0x00000001, 0x000f1133, 0x00000000, 0x00001f04,
+	0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04,
+	0x00001f04, 0x00001f04, 0x00001f04, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00010000, 0x00030404,
+	0x00000002, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x01010000,
+	0x01000000, 0x03030000, 0x00010303, 0x01020202,
+	0x00000000, 0x02040101, 0x21002103, 0x00061200,
+	0x06120612, 0x00000642, 0x00000000, 0x00000004,
+	0x00000000, 0x00000080, 0x00000000, 0x00000000,
+	0x00000000, 0xffffffff
+};
+
+void lowlevel_init(void)
+{
+	struct mxs_pinctrl_regs *pinctrl_regs =
+		(struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE;
+
+	/* Set EMI drive strength */
+	writel(0x00003fff, &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_clr);
+	writel(0x00002aaa, &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set);
+
+	mxs_common_spl_init(0, NULL, iomux_setup, ARRAY_SIZE(iomux_setup));
+}
diff --git a/board/liebherr/xea/xea.c b/board/liebherr/xea/xea.c
new file mode 100644
index 0000000000..1d47f67a7f
--- /dev/null
+++ b/board/liebherr/xea/xea.c
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * XEA iMX28 board
+ *
+ * Copyright (C) 2019 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * Copyright (C) 2018 DENX Software Engineering
+ * Måns Rullgård, DENX Software Engineering, mans@mansr.com
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/mii.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <errno.h>
+#include <usb.h>
+#include <serial.h>
+
+#ifdef CONFIG_SPL_BUILD
+#include <spl.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Functions
+ */
+
+static void init_clocks(void)
+{
+	/* IO0 clock at 480MHz */
+	mxs_set_ioclk(MXC_IOCLK0, 480000);
+	/* IO1 clock at 480MHz */
+	mxs_set_ioclk(MXC_IOCLK1, 480000);
+
+	/* SSP0 clock at 96MHz */
+	mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
+	/* SSP2 clock at 160MHz */
+	mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
+	/* SSP3 clock at 96MHz */
+	mxs_set_sspclk(MXC_SSPCLK3, 96000, 0);
+}
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong arg)
+{
+	init_clocks();
+	preloader_console_init();
+}
+
+static int boot_tiva0, boot_tiva1;
+
+/* Check if TIVAs request booting via U-Boot proper */
+void spl_board_init(void)
+{
+	struct gpio_desc btiva0, btiva1;
+	int ret;
+
+	ret = dm_gpio_lookup_name("GPIO0_23", &btiva0);
+	if (ret)
+		printf("Cannot get GPIO0_23\n");
+
+	ret = dm_gpio_lookup_name("GPIO0_25", &btiva1);
+	if (ret)
+		printf("Cannot get GPIO0_25\n");
+
+	ret = dm_gpio_request(&btiva0, "boot-tiva0");
+	if (ret)
+		printf("Cannot request GPIO0_23\n");
+
+	ret = dm_gpio_request(&btiva1, "boot-tiva1");
+	if (ret)
+		printf("Cannot request GPIO0_25\n");
+
+	dm_gpio_set_dir_flags(&btiva0, GPIOD_IS_IN);
+	dm_gpio_set_dir_flags(&btiva1, GPIOD_IS_IN);
+
+	udelay(1000);
+
+	boot_tiva0 = dm_gpio_get_value(&btiva0);
+	boot_tiva1 = dm_gpio_get_value(&btiva1);
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	spl_boot_list[0] = BOOT_DEVICE_MMC1;
+	spl_boot_list[1] = BOOT_DEVICE_SPI;
+}
+
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+
+	debug("%s: btiva0: %d btiva1: %d\n", __func__, boot_tiva0, boot_tiva1);
+	return !boot_tiva0 || !boot_tiva1;
+}
+#else
+
+int board_early_init_f(void)
+{
+	init_clocks();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	struct gpio_desc phy_rst;
+	int ret;
+
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	cpu_eth_init(NULL);
+
+	/* PHY INT#/PWDN# */
+	ret = dm_gpio_lookup_name("GPIO4_13", &phy_rst);
+	if (ret) {
+		printf("Cannot get GPIO4_13\n");
+		return ret;
+	}
+
+	ret = dm_gpio_request(&phy_rst, "phy-rst");
+	if (ret) {
+		printf("Cannot request GPIO4_13\n");
+		return ret;
+	}
+
+	dm_gpio_set_dir_flags(&phy_rst, GPIOD_IS_IN);
+	udelay(1000);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	return mxs_dram_init();
+}
+
+#endif	/* CONFIG_SPL_BUILD */
diff --git a/configs/imx28_xea_defconfig b/configs/imx28_xea_defconfig
new file mode 100644
index 0000000000..aaa7e31a93
--- /dev/null
+++ b/configs/imx28_xea_defconfig
@@ -0,0 +1,108 @@
+CONFIG_ARM=y
+CONFIG_SPL_SYS_THUMB_BUILD=y
+CONFIG_ARCH_MX28=y
+CONFIG_SYS_TEXT_BASE=0x40002000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x800
+CONFIG_SPL_DM_SPI=y
+CONFIG_TARGET_XEA=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0x1000
+CONFIG_FIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0
+CONFIG_SUPPORT_EMMC_BOOT_OVERRIDE_PART_CONFIG=y
+CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_DM_GPIO=y
+CONFIG_SPL_FORCE_MMC_BOOT=y
+CONFIG_SPL_MMC_TINY=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_PAYLOAD="u-boot.img"
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SPL=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+# CONFIG_CMD_PINMUX is not set
+CONFIG_CMD_SPI=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nor0=spi3.0"
+CONFIG_MTDPARTS_DEFAULT="spi3.0:64k(SPL),448k(uboot),128k(envs),384k(unused1),4096k(kernel),8192k(swupdate),-(unused2)"
+CONFIG_DOS_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx28-xea"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent interrupts"
+CONFIG_SPL_OF_PLATDATA=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USE_ENV_SPI_BUS=y
+CONFIG_ENV_SPI_BUS=3
+CONFIG_USE_ENV_SPI_CS=y
+CONFIG_ENV_SPI_CS=0
+CONFIG_USE_ENV_SPI_MAX_HZ=y
+CONFIG_ENV_SPI_MAX_HZ=40000000
+CONFIG_USE_ENV_SPI_MODE=y
+CONFIG_ENV_SPI_MODE=0x0
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_DEVRES=y
+CONFIG_DM_GPIO=y
+CONFIG_MXS_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_MXS=y
+CONFIG_MTD=y
+CONFIG_MTD_DEVICE=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=3
+CONFIG_SF_DEFAULT_MODE=0x0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ADDR=1
+CONFIG_PHY_FIXED=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MXS=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_CONS_INDEX=0
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MXS_SPI=y
+CONFIG_FS_FAT=y
+# CONFIG_SPL_OF_LIBFDT is not set
+# CONFIG_EFI_LOADER is not set
diff --git a/include/configs/xea.h b/include/configs/xea.h
new file mode 100644
index 0000000000..65109566d3
--- /dev/null
+++ b/include/configs/xea.h
@@ -0,0 +1,196 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * Copyright (C) 2018 DENX Software Engineering
+ * Måns Rullgård, DENX Software Engineering, mans@mansr.com
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ */
+#ifndef __CONFIGS_XEA_H__
+#define __CONFIGS_XEA_H__
+
+#include <linux/sizes.h>
+
+#define CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+/* SPL */
+#define CONFIG_SPL_STACK		0x20000
+
+#define CONFIG_SYS_SPL_ARGS_ADDR	0x44000000
+
+#define CONFIG_SYS_SPI_KERNEL_OFFS	SZ_1M
+#define CONFIG_SYS_SPI_ARGS_OFFS	SZ_512K
+#define CONFIG_SYS_SPI_ARGS_SIZE	SZ_32K
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	(SZ_512K / 0x200)
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	(SZ_32K / 0x200)
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	(SZ_1M / 0x200)
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SPI_FLASH_MTD
+#endif
+
+/* Memory configuration */
+#define PHYS_SDRAM_1			0x40000000	/* Base address */
+#define PHYS_SDRAM_1_SIZE		0x10000000	/* Max 256 MB RAM */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* Environment */
+#define CONFIG_ENV_OVERWRITE
+
+/* Booting Linux */
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_BOOTARGS		"console=ttyAMA0,115200n8 "
+#define CONFIG_BOOTCOMMAND	"run ${bootpri} ; run ${bootsec}"
+#define CONFIG_LOADADDR		0x42000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* Extra Environment */
+#define CONFIG_PREBOOT		"run prebootcmd"
+#define CONFIG_HOSTNAME		"xea"
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"bootmode=update\0"						\
+	"bootpri=mmc_mmc\0"						\
+	"bootsec=sf_swu\0"						\
+	"consdev=ttyAMA0\0"						\
+	"baudrate=115200\0"						\
+	"dtbaddr=0x44000000\0"						\
+	"dtbfile=imx28-xea.dtb\0"					\
+	"rootdev=/dev/mmcblk0p2\0"					\
+	"netdev=eth0\0"							\
+	"rdaddr=0x43000000\0"						\
+	"swufile=swupdate.img\0"					\
+	"sf_kernel_offset=0x100000\0"					\
+	"sf_kernel_size=0x400000\0"					\
+	"sf_swu_offset=0x500000\0"					\
+	"sf_swu_size=0x800000\0"					\
+	"rootpath=/opt/eldk-5.5/armv5te/rootfs-qte-sdk\0"		\
+	"do_update_mmc="						\
+		"if mmc rescan ; then "					\
+		"mmc dev 0 ${update_mmc_part} ; "			\
+		"if dhcp ${hostname}/${update_filename} ; then "	\
+		"setexpr fw_sz ${filesize} / 0x200 ; "	/* SD block size */ \
+		"setexpr fw_sz ${fw_sz} + 1 ; "				\
+		"mmc write ${loadaddr} ${update_offset} ${fw_sz} ; "	\
+		"fi ; "							\
+		"fi\0"							\
+	"do_update_sf="							\
+		"if sf probe ; then "					\
+		"if dhcp ${hostname}/${update_filename} ; then "	\
+		"sf erase ${update_offset} +${filesize} ; "		\
+		"sf write ${loadaddr} ${update_offset} ${filesize} ; "	\
+		"fi ; "							\
+		"fi\0"							\
+	"update_spl_filename=u-boot.sb\0"				\
+	"update_spl="							\
+		"setenv update_filename ${update_spl_filename} ; "	\
+		"setenv update_offset 0 ; "				\
+		"run do_update_sf\0"					\
+	"update_uboot_filename=u-boot.img\0"				\
+	"update_uboot="							\
+		"setenv update_filename ${update_uboot_filename} ; "	\
+		"setenv update_offset 0x10000 ; "			\
+		"run do_update_sf ; "					\
+		"setenv update_mmc_part 1 ; "				\
+		"setenv update_offset 0 ; "				\
+		"run do_update_mmc\0"					\
+	"update_kernel_filename=uImage\0"				\
+	"update_kernel="						\
+		"setenv update_mmc_part 1 ; "				\
+		"setenv update_filename ${update_kernel_filename} ; "	\
+		"setenv update_offset 0x800 ; "				\
+		"run do_update_mmc ; "					\
+		"setenv update_filename ${dtbfile} ; "			\
+		"setenv update_offset 0x400 ; "				\
+		"run do_update_mmc\0"					\
+	"update_sfkernel="						\
+		"setenv update_filename fitImage ; "			\
+		"setenv update_offset ${sf_kernel_offset} ; "		\
+		"run do_update_sf\0"					\
+	"update_swu="							\
+		"setenv update_filename ${swufile} ; "			\
+		"setenv update_offset ${sf_swu_offset} ; "		\
+		"run do_update_sf\0"					\
+	"addcons="							\
+		"setenv bootargs ${bootargs} "				\
+		"console=${consdev},${baudrate}\0"			\
+	"addip="							\
+		"setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:"		\
+			"${netmask}:${hostname}:${netdev}:off\0"	\
+	"addmisc="							\
+		"setenv bootargs ${bootargs} ${miscargs}\0"		\
+	"addargs=run addcons addmisc\0"					\
+	"mmcload="							\
+		"mmc rescan ; "						\
+		"mmc dev 0 1 ; "					\
+		"mmc read ${loadaddr} 0x800 0x2000 ; "			\
+		"mmc read ${dtbaddr} 0x400 0x80\0"			\
+	"netload="							\
+		"dhcp ${loadaddr} ${hostname}/${bootfile} ; "		\
+		"tftp ${dtbaddr} ${hostname}/${dtbfile}\0"		\
+	"sfload="							\
+		"sf probe ; "						\
+		"sf read ${loadaddr} ${sf_kernel_offset} ${sf_kernel_size}\0" \
+	"usbload="							\
+		"usb start ; "						\
+		"load usb 0:1 ${loadaddr} ${bootfile}\0"		\
+	"miscargs=panic=1\0"						\
+	"mmcargs=setenv bootargs root=${rootdev} rw rootwait\0"		\
+	"nfsargs="							\
+		"setenv bootargs root=/dev/nfs rw "			\
+			"nfsroot=${serverip}:${rootpath},v3,tcp\0"	\
+	"mmc_mmc="							\
+		"if run mmcload mmcargs addargs ; then "		\
+		"bootm ${loadaddr} - ${dtbaddr} ; "			\
+		"fi\0"							\
+	"mmc_nfs="							\
+		"if run mmcload nfsargs addip addargs ; then "		\
+		"bootm ${loadaddr} - ${dtbaddr} ; "			\
+		"fi\0"							\
+	"sf_mmc="							\
+		"if run sfload mmcargs addargs ; then "			\
+		"bootm ${loadaddr} - ${dtbaddr} ; "			\
+		"fi\0"							\
+	"sf_swu="							\
+		"if run sfload ; then "					\
+		"sf read ${rdaddr} ${sf_swu_offset} ${sf_swu_size} ; "	\
+		"setenv bootargs root=/dev/ram0 rw ; "			\
+		"run addargs ; "					\
+		"bootm ${loadaddr} ${rdaddr} ; "		\
+		"fi\0"							\
+	"net_mmc="							\
+		"if run netload mmcargs addargs ; then "		\
+		"bootm ${loadaddr} - ${dtbaddr} ; "			\
+		"fi\0"							\
+	"net_nfs="							\
+		"if run netload nfsargs addip addargs ; then "		\
+		"bootm ${loadaddr} - ${dtbaddr} ; "			\
+		"fi\0"							\
+	"prebootcmd="							\
+		"if test \"${envsaved}\" != y ; then ; "		\
+		"setenv envsaved y ; "					\
+		"saveenv ; "						\
+		"fi ; "							\
+		"if test \"${bootmode}\" = normal ; then "		\
+		"setenv bootdelay 0 ; "					\
+		"setenv bootpri mmc_mmc ; "				\
+		"elif test \"${bootmode}\" = devel ; then "		\
+		"setenv bootdelay 3 ; "					\
+		"setenv bootpri net_mmc ; "				\
+		"else "							\
+		"if test \"${bootmode}\" != update ; then "		\
+		"echo Warning: unknown bootmode \"${bootmode}\" ; "	\
+		"fi ; "							\
+		"setenv bootdelay 1 ; "					\
+		"setenv bootpri sf_swu ; "				\
+		"fi\0"
+
+/* The rest of the configuration is shared */
+#include <configs/mxs.h>
+
+#endif /* __CONFIGS_XEA_H__ */
