From patchwork Tue Nov 26 01:06:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 1200701 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47MQjD6t7hz9s3Z for ; Tue, 26 Nov 2019 12:06:56 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 87C70C21E88; Tue, 26 Nov 2019 01:06:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: * X-Spam-Status: No, score=1.4 required=5.0 tests=RCVD_IN_SORBS_WEB, UPPERCASE_50_75 autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6A0ACC21D56; Tue, 26 Nov 2019 01:06:52 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 94026C21D56; Tue, 26 Nov 2019 01:06:50 +0000 (UTC) Received: from regular1.263xmail.com (regular1.263xmail.com [211.150.70.200]) by lists.denx.de (Postfix) with ESMTPS id E95A8C21C27 for ; Tue, 26 Nov 2019 01:06:49 +0000 (UTC) Received: from localhost (unknown [192.168.167.8]) by regular1.263xmail.com (Postfix) with ESMTP id 1F328327; Tue, 26 Nov 2019 09:06:47 +0800 (CST) X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ADDR-CHECKED4: 1 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P11241T140546505705216S1574730406127074_; Tue, 26 Nov 2019 09:06:47 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: <30905993037a25d46d5277378e5506f5> X-RL-SENDER: david.wu@rock-chips.com X-SENDER: wdc@rock-chips.com X-LOGIN-NAME: david.wu@rock-chips.com X-FST-TO: u-boot@lists.denx.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 From: David Wu To: u-boot@lists.denx.de Date: Tue, 26 Nov 2019 09:06:42 +0800 Message-Id: <20191126010643.7218-1-david.wu@rock-chips.com> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 Cc: David Wu Subject: [U-Boot] [PATCH 1/2] arm: rockchip: rk3308: Initialize the iomux configuration X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" When we want to use plus iomux feature, we need to enable them at spl. Signed-off-by: David Wu --- arch/arm/mach-rockchip/rk3308/rk3308.c | 33 ++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/mach-rockchip/rk3308/rk3308.c b/arch/arm/mach-rockchip/rk3308/rk3308.c index f27f9e8c0b..bd99899094 100644 --- a/arch/arm/mach-rockchip/rk3308/rk3308.c +++ b/arch/arm/mach-rockchip/rk3308/rk3308.c @@ -72,6 +72,11 @@ enum { UART2_IO_SEL_M1, UART2_IO_SEL_USB, + GPIO2C0_SEL_SRC_CTRL_SHIFT = 11, + GPIO2C0_SEL_SRC_CTRL_MASK = BIT(11), + GPIO2C0_SEL_SRC_CTRL_IOMUX = 0, + GPIO2C0_SEL_SRC_CTRL_SEL_PLUS, + GPIO3B3_SEL_SRC_CTRL_SHIFT = 7, GPIO3B3_SEL_SRC_CTRL_MASK = BIT(7), GPIO3B3_SEL_SRC_CTRL_IOMUX = 0, @@ -97,6 +102,18 @@ enum { GPIO3B2_SEL_PLUS_EMMC_RSTN, GPIO3B2_SEL_PLUS_SPI1_MISO, GPIO3B2_SEL_PLUS_LCDC_D22_M1, + + I2C3_IOFUNC_SRC_CTRL_SHIFT = 10, + I2C3_IOFUNC_SRC_CTRL_MASK = BIT(10), + I2C3_IOFUNC_SRC_CTRL_SEL_PLUS = 1, + + GPIO2A3_SEL_SRC_CTRL_SHIFT = 7, + GPIO2A3_SEL_SRC_CTRL_MASK = BIT(7), + GPIO2A3_SEL_SRC_CTRL_SEL_PLUS = 1, + + GPIO2A2_SEL_SRC_CTRL_SHIFT = 3, + GPIO2A2_SEL_SRC_CTRL_MASK = BIT(3), + GPIO2A2_SEL_SRC_CTRL_SEL_PLUS = 1, }; enum { @@ -166,10 +183,26 @@ __weak void board_debug_uart_init(void) int arch_cpu_init(void) { static struct rk3308_sgrf * const sgrf = (void *)SGRF_BASE; + static struct rk3308_grf * const grf = (void *)GRF_BASE; /* Set CRYPTO SDMMC EMMC NAND SFC USB master bus to be secure access */ rk_clrreg(&sgrf->con_secure0, 0x2b83); + + rk_clrsetreg(&grf->soc_con13, + I2C3_IOFUNC_SRC_CTRL_MASK | GPIO2A3_SEL_SRC_CTRL_MASK | + GPIO2A2_SEL_SRC_CTRL_MASK, + I2C3_IOFUNC_SRC_CTRL_SEL_PLUS << I2C3_IOFUNC_SRC_CTRL_SHIFT | + GPIO2A3_SEL_SRC_CTRL_SEL_PLUS << GPIO2A3_SEL_SRC_CTRL_SHIFT | + GPIO2A2_SEL_SRC_CTRL_SEL_PLUS << GPIO2A2_SEL_SRC_CTRL_SHIFT); + + rk_clrsetreg(&grf->soc_con15, + GPIO2C0_SEL_SRC_CTRL_MASK | GPIO3B3_SEL_SRC_CTRL_MASK | + GPIO3B2_SEL_SRC_CTRL_MASK, + GPIO2C0_SEL_SRC_CTRL_SEL_PLUS << GPIO2C0_SEL_SRC_CTRL_SHIFT | + GPIO3B3_SEL_SRC_CTRL_SEL_PLUS << GPIO3B3_SEL_SRC_CTRL_SHIFT | + GPIO3B3_SEL_SRC_CTRL_SEL_PLUS << GPIO3B2_SEL_SRC_CTRL_SHIFT); + return 0; } #endif