From patchwork Fri Nov 22 22:44:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Olovyannikov X-Patchwork-Id: 1199707 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=broadcom.com header.i=@broadcom.com header.b="VCSNKyrD"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47KWjS2NHVz9sPc for ; Sat, 23 Nov 2019 09:45:32 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 0B0DBC21E3B; Fri, 22 Nov 2019 22:45:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 06C16C21DDC; Fri, 22 Nov 2019 22:45:11 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 9122FC21D8A; Fri, 22 Nov 2019 22:45:06 +0000 (UTC) Received: from mail-wm1-f67.google.com (mail-wm1-f67.google.com [209.85.128.67]) by lists.denx.de (Postfix) with ESMTPS id 5DBDBC21C29 for ; Fri, 22 Nov 2019 22:45:06 +0000 (UTC) Received: by mail-wm1-f67.google.com with SMTP id x26so8833031wmk.4 for ; Fri, 22 Nov 2019 14:45:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+MGjrAcP0z9DnElo1nSabx58bfgoN0DNMj2i5Ld2DyI=; b=VCSNKyrD7imS++8475cjTdHuCT9HHdBpVokK8UKFDjWEggR98qXP1+/9Fp6SFb/DbV 6GvpEr1updkrUyBRj/EhuEWQOai7LPUlV8Y+GSWEpiUJWkZN6cVMf6qLBwimZigiQ/Xc pT5RSbyxhU+JaUwtguBXeyCCJFS0tmxUaOlME= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+MGjrAcP0z9DnElo1nSabx58bfgoN0DNMj2i5Ld2DyI=; b=mswxD3EyVfsVFCylUtd5s2fWxjGHAljm6NF4H4wYLcbckWKjOHh8wQax/hw+DXt13h IlynYVJZ44zqb+h7Kdwq/sOAq9Ne1qY+w0xYeBUFupUzMvbtpxn/dCdZ7FcTILgamGDP e6SDOHPg3puTF7uRm4ZLUznBnrijrdQvih7s/k99MiZufJPSQ68IyOkIZxNty79O8vC4 gxrSA5fuK95LXzmcHQKzVV5LCgAOPVrzfwOGmxEXqwrGnHtV2OpW4dlS/a0HFTHgDS32 8Vs/viC2PpE0R47X040Gjp6VfzJJjVB6d6u9EmS4gc2OU7jPJUMAPoejPlMIqCm1D7oO E3ew== X-Gm-Message-State: APjAAAWNC1m5deTcdhmRSFj9bdS5UJr2O0jgVYMN/vC4mU35+74/fySp mr6+vySp6q31ilvdCHliT8L3c7R643OtMPSbR6KkZPTPx69CyiFVTSlM2ezVividoxr8T6X3C+6 OA2Ka2RTJfKf7LvWDkD1An+/qeGAyLOomZjIqXJYATAucCgG0CnaUI2IOfL+LJyg2TvMaiGytLa D2oOaKrB1QwkM= X-Google-Smtp-Source: APXvYqx4SmcWnFqysi7Ywtv07TjlbWD+0FoRQjYgHTJyNehIWnI1Xm8Wt2bv3eJKjr/Mr4AopAobRQ== X-Received: by 2002:a05:600c:299:: with SMTP id 25mr19180566wmk.50.1574462705523; Fri, 22 Nov 2019 14:45:05 -0800 (PST) Received: from LBRMN-LNXUB114.ric.broadcom.com ([192.19.228.250]) by smtp.gmail.com with ESMTPSA id b15sm9143223wrx.77.2019.11.22.14.45.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Nov 2019 14:45:05 -0800 (PST) From: Vladimir Olovyannikov To: u-boot@lists.denx.de Date: Fri, 22 Nov 2019 14:44:41 -0800 Message-Id: <20191122224443.29497-2-vladimir.olovyannikov@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191122224443.29497-1-vladimir.olovyannikov@broadcom.com> References: <20191122224443.29497-1-vladimir.olovyannikov@broadcom.com> Cc: Rayagonda Kokatanur Subject: [U-Boot] [PATCH 1/3] pinctrl: pinctrl-single: Handle different register width X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Rayagonda Kokatanur Add support to use different register read/write api's based on register width. Signed-off-by: Rayagonda Kokatanur Signed-off-by: Vladimir Olovyannikov --- drivers/pinctrl/pinctrl-single.c | 111 ++++++++++++++++++++++--------- 1 file changed, 80 insertions(+), 31 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 1dfc97dcea..6c6a33e4c5 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -11,12 +11,23 @@ DECLARE_GLOBAL_DATA_PTR; +/** + * struct single_pdata - pinctrl device instance + * @base first configuration register + * @offset index of last configuration register + * @mask configuration-value mask bits + * @width configuration register bit width + * @read register read function to use + * @write register write function to use + */ struct single_pdata { - fdt_addr_t base; /* first configuration register */ - int offset; /* index of last configuration register */ - u32 mask; /* configuration-value mask bits */ - int width; /* configuration register bit width */ + void __iomem *base; + int offset; + u32 mask; + int width; bool bits_per_mux; + u32 (*read)(void __iomem *reg); + void (*write)(u32 val, void __iomem *reg); }; struct single_fdt_pin_cfg { @@ -30,6 +41,36 @@ struct single_fdt_bits_cfg { fdt32_t mask; /* configuration register mask */ }; +static u32 __maybe_unused single_readb(void __iomem *reg) +{ + return readb(reg); +} + +static u32 __maybe_unused single_readw(void __iomem *reg) +{ + return readw(reg); +} + +static u32 __maybe_unused single_readl(void __iomem *reg) +{ + return readl(reg); +} + +static void __maybe_unused single_writeb(u32 val, void __iomem *reg) +{ + writeb(val, reg); +} + +static void __maybe_unused single_writew(u32 val, void __iomem *reg) +{ + writew(val, reg); +} + +static void __maybe_unused single_writel(u32 val, void __iomem *reg) +{ + writel(val, reg); +} + /** * single_configure_pins() - Configure pins based on FDT data * @@ -55,24 +96,15 @@ static int single_configure_pins(struct udevice *dev, for (n = 0; n < count; n++, pins++) { reg = fdt32_to_cpu(pins->reg); - if ((reg < 0) || (reg > pdata->offset)) { + if (reg > pdata->offset) { dev_dbg(dev, " invalid register offset 0x%pa\n", ®); continue; } - reg += pdata->base; + reg += (phys_addr_t)pdata->base; val = fdt32_to_cpu(pins->val) & pdata->mask; - switch (pdata->width) { - case 16: - writew((readw(reg) & ~pdata->mask) | val, reg); - break; - case 32: - writel((readl(reg) & ~pdata->mask) | val, reg); - break; - default: - dev_warn(dev, "unsupported register width %i\n", - pdata->width); - continue; - } + val |= pdata->read((void __iomem *)reg) & ~pdata->mask; + pdata->write(val, (void __iomem *)reg); + dev_dbg(dev, " reg/val 0x%pa/0x%08x\n", ®, val); } return 0; @@ -97,19 +129,9 @@ static int single_configure_bits(struct udevice *dev, mask = fdt32_to_cpu(pins->mask); val = fdt32_to_cpu(pins->val) & mask; + val |= pdata->read((void __iomem *)reg) & ~mask; + pdata->write(val, (void __iomem *)reg); - switch (pdata->width) { - case 16: - writew((readw(reg) & ~mask) | val, reg); - break; - case 32: - writel((readl(reg) & ~mask) | val, reg); - break; - default: - dev_warn(dev, "unsupported register width %i\n", - pdata->width); - continue; - } dev_dbg(dev, " reg/val 0x%pa/0x%08x\n", ®, val); } return 0; @@ -153,6 +175,32 @@ static int single_set_state(struct udevice *dev, return len; } +static int single_probe(struct udevice *dev) +{ + struct single_pdata *pdata = dev->platdata; + + switch (pdata->width) { + case 8: + pdata->read = single_readb; + pdata->write = single_writeb; + break; + case 16: + pdata->read = single_readw; + pdata->write = single_writew; + break; + case 32: + pdata->read = single_readl; + pdata->write = single_writel; + break; + default: + dev_warn(dev, "%s: unsupported register width %d\n", + __func__, pdata->width); + return -EINVAL; + } + + return 0; +} + static int single_ofdata_to_platdata(struct udevice *dev) { fdt_addr_t addr; @@ -174,7 +222,7 @@ static int single_ofdata_to_platdata(struct udevice *dev) dev_dbg(dev, "no valid base register address\n"); return -EINVAL; } - pdata->base = addr; + pdata->base = (void __iomem *)addr; pdata->mask = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "pinctrl-single,function-mask", @@ -201,4 +249,5 @@ U_BOOT_DRIVER(single_pinctrl) = { .ops = &single_pinctrl_ops, .platdata_auto_alloc_size = sizeof(struct single_pdata), .ofdata_to_platdata = single_ofdata_to_platdata, + .probe = single_probe, };