@@ -332,6 +332,7 @@
compatible = "altr,socfpga-gate-clk";
clocks = <&mainclk>, <&per_base_clk>;
div-reg = <0x64 4 3>;
+ src-reg = <0x70 0 1>;
clk-gate = <0x60 2>;
};
@@ -340,6 +341,7 @@
compatible = "altr,socfpga-gate-clk";
clocks = <&mainclk>, <&per_base_clk>;
div-reg = <0x64 7 3>;
+ src-reg = <0x70 1 1>;
clk-gate = <0x60 3>;
};
@@ -453,6 +455,7 @@
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+ src-reg = <0xac 0 2>;
clk-gate = <0xa0 8>;
clk-phase = <0 135>;
};
@@ -469,6 +472,7 @@
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+ src-reg = <0xac 2 2>;
clk-gate = <0xa0 9>;
};
@@ -491,6 +495,7 @@
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
+ src-reg = <0xac 4 2>;
clk-gate = <0xa0 11>;
};
For some clocks, the socfpga gen5 clock driver in preparation needs a source register, which is used to select the parent clock. Add these to the socfpga gen5 base device tree. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> --- Changes in v2: - split this patch from v1 5/6 arch/arm/dts/socfpga.dtsi | 5 +++++ 1 file changed, 5 insertions(+)