From patchwork Fri Oct 4 22:30:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dalon L Westergreen X-Patchwork-Id: 1172063 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46lPpF6xpHz9sNw for ; Sat, 5 Oct 2019 08:35:17 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 80529C21EA1; Fri, 4 Oct 2019 22:32:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id C8C53C21F35; Fri, 4 Oct 2019 22:31:30 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 84E73C21EE7; Fri, 4 Oct 2019 22:31:04 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lists.denx.de (Postfix) with ESMTPS id 8021AC21F0F for ; Fri, 4 Oct 2019 22:31:00 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 Oct 2019 15:31:00 -0700 X-IronPort-AV: E=Sophos;i="5.67,257,1566889200"; d="scan'208";a="217306490" Received: from dwesterg-mobl.amr.corp.intel.com (HELO dwesterg-mobl1.amr.corp.intel.com) ([10.251.26.183]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 Oct 2019 15:30:59 -0700 From: Dalon Westergreen To: u-boot@lists.denx.de, tien.fong.chee@intel.com, simon.k.r.goldschmidt@gmail.com, marex@denx.de, dinguyen@kernel.org, ley.foon.tan@intel.com, chin.liang.see@intel.com Date: Fri, 4 Oct 2019 15:30:43 -0700 Message-Id: <20191004223043.18127-9-dalon.westergreen@linux.intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191004223043.18127-1-dalon.westergreen@linux.intel.com> References: <20191004223043.18127-1-dalon.westergreen@linux.intel.com> MIME-Version: 1.0 Subject: [U-Boot] [PATCH 8/8] ARM: socfpga: Update README.socfpga to add qts-filter-a10 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Dalon Westergreen Update the readme to add a simple description of using the qts-filter-a10.sh script. Signed-off-by: Dalon Westergreen --- doc/README.socfpga | 37 +++++++++++++++++++++++++++++++++---- 1 file changed, 33 insertions(+), 4 deletions(-) diff --git a/doc/README.socfpga b/doc/README.socfpga index cae0ef1a21..c5a3b11133 100644 --- a/doc/README.socfpga +++ b/doc/README.socfpga @@ -16,9 +16,9 @@ controller support within SOCFPGA #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 -> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM --------------------------------------------------- -Generating the handoff header files for U-Boot SPL --------------------------------------------------- +--------------------------------------------------------------------- +Cyclone5 / Arria 5 Generating the handoff header files for U-Boot SPL +--------------------------------------------------------------------- This text is assuming quartus 16.1, but newer versions will probably work just fine too; verified with DE1_SOC_Linux_FB demo project (https://github.com/VCTLabs/DE1_SOC_Linux_FB). @@ -32,7 +32,7 @@ Rebuilding your Quartus project Choose one of the follwing methods, either command line or GUI. -Using the comaand line +Using the command line ~~~~~~~~~~~~~~~~~~~~~~ First run the embedded command shell, using your path to the Quartus install: @@ -147,3 +147,32 @@ Note: file sizes will differ slightly depending on the selected board. Now your board is ready for full mainline support including U-Boot SPL. The Preloader will not be needed any more. + +---------------------------------------------------------- +Arria10 Generating the handoff header files for U-Boot SPL +---------------------------------------------------------- + +A header file for inclusion in a devicetree for Arria10 can be generated +by the qts-filter-a10.sh script directly from the hps_isw_handoff/hps.xml +file generated during the FPGA project compilation. The header contains +all PLL, clock, pinmux, and bridge configurations required. + +Please look at the socfpga_arria10_socdk_sdmmc-u-boot.dtsi for an example +that includes use of the generated handoff header. + +Devicetree header generation +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The qts-filter-a10.sh script can process the compile time genetated hps.xml +to create the appropriate devicetree header. + + + $ ./arch/arm/mach-socfpga/qts-filter-a10.sh \ + \ + + + hps_xml - hps_isw_handoff/hps.xml from Quartus project + output_file - Output filename and location for header file + +The script generates a single header file names that should +be placed in arch/arm/dts.