From patchwork Fri Sep 6 06:04:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yangbo Lu X-Patchwork-Id: 1158768 X-Patchwork-Delegate: van.freenix@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46Pn8h3CHpz9sN1 for ; Fri, 6 Sep 2019 16:05:08 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id F0A76C21E18; Fri, 6 Sep 2019 06:03:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6E988C21E13; Fri, 6 Sep 2019 06:03:38 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id D0A17C21E0B; Fri, 6 Sep 2019 06:03:11 +0000 (UTC) Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by lists.denx.de (Postfix) with ESMTPS id DC04AC21DD9 for ; Fri, 6 Sep 2019 06:03:09 +0000 (UTC) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id A96A820057B; Fri, 6 Sep 2019 08:03:09 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 9B3AD20056A; Fri, 6 Sep 2019 08:03:07 +0200 (CEST) Received: from localhost.localdomain (mega.ap.freescale.net [10.192.208.232]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id F1DBE402A5; Fri, 6 Sep 2019 14:03:04 +0800 (SGT) From: Yangbo Lu To: u-boot@lists.denx.de, Peng Fan Date: Fri, 6 Sep 2019 14:04:58 +0800 Message-Id: <20190906060458.10561-4-yangbo.lu@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190906060458.10561-1-yangbo.lu@nxp.com> References: <20190906060458.10561-1-yangbo.lu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [U-Boot] [v2, 3/3] mmc: fsl_esdhc: rename fsl_esdhc_init to fsl_esdhc_get_cfg X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" For non-DM code, below functions had similar names. - fsl_esdhc_initialize - fsl_esdhc_mmc_init - fsl_esdhc_init However fsl_esdhc_init was mainly used to get cfg. So rename it to fsl_esdhc_get_cfg. Fix up bus-width capability handling, and drop controller initialization because it will be re-initialized in later esdhc_init_common for DM or esdhc_init for non-DM when use it. Signed-off-by: Yangbo Lu --- Changes for v2: - Rebased. --- drivers/mmc/fsl_esdhc.c | 68 ++++++++----------------------------------------- 1 file changed, 11 insertions(+), 57 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 3b079f1..03a7e89 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -25,14 +25,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define ESDHC_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ - IRQSTATEN_DINT | IRQSTATEN_BWR | \ - IRQSTATEN_BRR | IRQSTATEN_CINT | \ - IRQSTATEN_CTOE | IRQSTATEN_CCE | \ - IRQSTATEN_CEBE | IRQSTATEN_CIE | \ - IRQSTATEN_DTOE | IRQSTATEN_DCE | \ - IRQSTATEN_DEBE) - struct fsl_esdhc { uint dsaddr; /* SDMA system address register */ uint blkattr; /* Block attributes register */ @@ -651,57 +643,25 @@ static int esdhc_getcd_common(struct fsl_esdhc_priv *priv) return timeout > 0; } -static int esdhc_reset(struct fsl_esdhc *regs) -{ - ulong start; - - /* reset the controller */ - esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); - - /* hardware clears the bit when it is done */ - start = get_timer(0); - while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) { - if (get_timer(start) > 100) { - printf("MMC/SD: Reset never completed.\n"); - return -ETIMEDOUT; - } - } - - return 0; -} - #if !CONFIG_IS_ENABLED(DM_MMC) static const struct mmc_ops esdhc_ops; #endif -static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, - struct fsl_esdhc_plat *plat) +static int fsl_esdhc_get_cfg(struct fsl_esdhc_priv *priv, + struct fsl_esdhc_plat *plat) { + struct fsl_esdhc *regs = priv->esdhc_regs; + u32 caps, voltage_caps = 0; struct mmc_config *cfg; - struct fsl_esdhc *regs; - u32 caps, voltage_caps; - int ret; if (!priv) return -EINVAL; - regs = priv->esdhc_regs; - - /* First reset the eSDHC controller */ - ret = esdhc_reset(regs); - if (ret) - return ret; - - esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN | - SYSCTL_IPGEN | SYSCTL_CKEN); - - writel(ESDHC_IRQ_EN_BITS, ®s->irqstaten); cfg = &plat->cfg; #ifndef CONFIG_DM_MMC memset(cfg, '\0', sizeof(*cfg)); #endif - voltage_caps = 0; caps = esdhc_read32(®s->hostcapblt); #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 @@ -739,18 +699,10 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, else if (priv->bus_width == 4) cfg->host_caps = MMC_MODE_4BIT; - cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE cfg->host_caps |= MMC_MODE_DDR_52MHz; #endif - if (priv->bus_width > 0) { - if (priv->bus_width < 8) - cfg->host_caps &= ~MMC_MODE_8BIT; - if (priv->bus_width < 4) - cfg->host_caps &= ~MMC_MODE_4BIT; - } - if (caps & HOSTCAPBLT2_HSS) cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; @@ -761,7 +713,6 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, cfg->f_min = 400000; cfg->f_max = min(priv->sdhc_clk, (u32)200000000); - cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; return 0; @@ -884,7 +835,10 @@ static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg, return -EINVAL; priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base); - priv->bus_width = cfg->max_bus_width; + if (cfg->max_bus_width) + priv->bus_width = cfg->max_bus_width; + else + priv->bus_width = 4; priv->sdhc_clk = cfg->sdhc_clk; priv->wp_enable = cfg->wp_enable; @@ -919,7 +873,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) return ret; } - ret = fsl_esdhc_init(priv, plat); + ret = fsl_esdhc_get_cfg(priv, plat); if (ret) { debug("%s init failure\n", __func__); free(plat); @@ -1014,9 +968,9 @@ static int fsl_esdhc_probe(struct udevice *dev) } } - ret = fsl_esdhc_init(priv, plat); + ret = fsl_esdhc_get_cfg(priv, plat); if (ret) { - dev_err(dev, "fsl_esdhc_init failure\n"); + dev_err(dev, "fsl_esdhc_get_cfg failure\n"); return ret; }