From patchwork Wed Jul 31 11:51:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 1139695 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=public-files.de Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.b="AeroNegp"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45zBcQ32Dpz9s00 for ; Wed, 31 Jul 2019 21:52:20 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id A7B7FC21E1E; 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Wed, 31 Jul 2019 13:52:00 +0200 From: Frank Wunderlich To: Albert Aribaud , Bao Xiaowei , Bin Meng , Christian Gmeiner , Hou Zhiqiang , Marek Vasut , Mark Lee , Oleksandr Rybalko , Prabhakar Kushwaha , Ryder Lee , Simon Glass , Stefan Roese , Tuomas Tynkkynen , u-boot@lists.denx.de, Weijie Gao Date: Wed, 31 Jul 2019 13:51:45 +0200 Message-Id: <20190731115145.22095-5-frank-w@public-files.de> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190731115145.22095-1-frank-w@public-files.de> References: <20190731115145.22095-1-frank-w@public-files.de> X-Provags-ID: V03:K1:mdpp5sG8u3g41s7QKrY9EQjhgQfd16Ag2nfn+P7VYTgM9TcNqvi e7w316xQPdH1prVcixMWD4xgLkbLdEmBlOU/+GPAWS1lA32JKqSpwbEMTZWbO0HTpxP9Sx8 mfu3Qww5r49YdouFeKkbbo7a21gvoUz1iM+AqIW00TKDzc50ViJ7Nj5GO/MlA+rlMWmByS3 HoCe56WOfxNvK2WCEfsqg== X-UI-Out-Filterresults: notjunk:1; V03:K0:BmRIMe/L+Uw=:TNDOlYpoRRbzZpOEY/hvnZ jPKe3W4Uqi8G4TzQC1RbV1v4yCbx6ZlaezJEU8R45kFztvZiD1bMFgSJWuIuwlWK2GuDi1fxY UsF/ViD/2F4VEjTvYyz6vspw4FVvqsn43dc8ShMC3r+m6Jd1/G0iSipAgTy3QBA+rvdNQTS+U vAFAcLqMi97PRl2uFq6gztY0pXyd1A2jU0MYWcIhe4qaGveAoR5Uv1+KFoVaTFa196n7sYakR K42/UtcWlKNw/T75v30mzEyTkWXiEI/1IfEvCwt0dl/8cBy1BXYA8L98jFE/dQfIn4N+SsZ0o IB15i5MWnL7Zzi97HqeuxWVHHZxNg433eAXfNCyZNfrvmqKcYwuiLqTHRR7ZYATt7RGVb1VXV 72fvgJQKfz3tevhk6nSLw4B4+z/2HLI55FwUQWEUKeRGRosk4QkctjZledCGmMjm5O81hEAKf eN+GnSQJFzf3xSXwWoDOhZCjtzX3O0MuOqNrDIodwo73pIXhwhFhOLZ7pMvgeqagHdJZ+xwnE OGy7foeQbIaekaK0qgq3DEBzeVHIle6vOz2E4Lv3h7NWW/lTGK8j/upD9+IjMZSpMxF80LHOY ViUGbCEHLxTejerBIC8Z2GrIJUyqb6YA0KvyqGDxM9eN1Din3q34fjyURmQtGC1aOINZVzw20 Le22Nbq9RVNkvfvytH+LWBa0wNincsGm8S4r/tbZD6O3tqA645qIydkkbeyszVQcCeH3RETv0 ej9qOBi9NmNTCk+0TZR7CEjQVscPo5jgLXN1zob4BQC9uCH6B7hdizBIaTAVXVTwuGb2GoHGc oltleQ5xOL2HINoUQJ6IRu+GFwH/n0hyk6xnsd1G3wEFOr/PVBTgoMaCIWAFP0U6lWZe0W0tg mxMzck0A09Ac83FjTCediCYY40TR+5M6QWb9YBnfDdkkDzUuydMclDCUbjUpOxYjLjmZS+U8Y KbEK/8loFhIwmSmS8hlg/IX+78jyHXjoxTiqJuPibtyBPk2+IXFdZYf+GMImLSQd+eD0W3aEH mDtZz05QvG+6Rm8bFESmC775d7xp2hclXU4GY8fXHWQEG90XbuZskMQEJ0+2+3bamlrMMuPxC Q4u+PfLoNqfkPE= Subject: [U-Boot] [PATCH 4/4] arm: dts: Add PCI-E controller for mt7623 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" this Patch adds pcie-controller node for mt7623 Signed-off-by: Frank Wunderlich --- arch/arm/dts/mt7623.dtsi | 108 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 108 insertions(+) -- 2.17.1 diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi index 64079c61bf..5d7c62bb8d 100644 --- a/arch/arm/dts/mt7623.dtsi +++ b/arch/arm/dts/mt7623.dtsi @@ -255,6 +255,114 @@ #reset-cells = <1>; }; + pcie: pcie-controller@1a140000 { + compatible = "mediatek,mt7623-pcie"; + device_type = "pci"; + reg = <0x1a140000 0x1000>, /* PCIe shared registers */ + <0x1a142000 0x1000>, /* Port0 registers */ + <0x1a143000 0x1000>, /* Port1 registers */ + <0x1a144000 0x1000>; /* Port2 registers */ + reg-names = "subsys", "port0", "port1", "port2"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 0>; + interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 + IRQ_TYPE_LEVEL_LOW>, + <0x0800 0 0 0 &sysirq GIC_SPI 194 + IRQ_TYPE_LEVEL_LOW>, + <0x1000 0 0 0 &sysirq GIC_SPI 195 + IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_ETHIF_SEL>, + <&hifsys CLK_HIFSYS_PCIE0>, + <&hifsys CLK_HIFSYS_PCIE1>, + <&hifsys CLK_HIFSYS_PCIE2>; + clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; + reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2"; + phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; + power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>; + bus-range = <0x00 0xff>; + status = "okay"; + ranges = <0x81000000 0 0x1a160000 0x1a160000 0 0x00010000 + 0x83000000 0 0x60000000 0x60000000 0 0x10000000>; + + pcie@0,0 { + device_type = "pci"; + reg = <0x0000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 + IRQ_TYPE_LEVEL_LOW>; + ranges; + num-lanes = <1>; + status = "disabled"; + }; + + pcie@1,0 { + device_type = "pci"; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 + IRQ_TYPE_LEVEL_LOW>; + ranges; + num-lanes = <1>; + status = "disabled"; + }; + + pcie@2,0 { + device_type = "pci"; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 + IRQ_TYPE_LEVEL_LOW>; + ranges; + num-lanes = <1>; + status = "disabled"; + }; + }; + + pcie0_phy: pcie-phy@1a149000 { + compatible = "mediatek,generic-tphy-v1"; + reg = <0x1a149000 0x0700>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + pcie0_port: pcie-phy@1a149900 { + reg = <0x1a149900 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + + pcie1_phy: pcie-phy@1a14a000 { + compatible = "mediatek,generic-tphy-v1"; + reg = <0x1a14a000 0x0700>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + pcie1_port: pcie-phy@1a14a900 { + reg = <0x1a14a900 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + ethsys: syscon@1b000000 { compatible = "mediatek,mt7623-ethsys", "syscon"; reg = <0x1b000000 0x1000>;