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[U-Boot,2/4] ata: ahci: Don't forget to clear upper address regs.

Message ID 20190731115145.22095-3-frank-w@public-files.de
State Superseded
Delegated to: Tom Rini
Headers show
Series add pcie/ahci for mt7623/bpi-r2 | expand

Commit Message

Frank Wunderlich July 31, 2019, 11:51 a.m. UTC 
From: Oleksandr Rybalko <ray@ddteam.net>

In 32bits mode upper bits need to be set to 0, otherwise controller will
try to DMA into not existing memory and stops with error.

Tested-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Oleksandr Rybalko <ray@ddteam.net>
---
 drivers/ata/ahci.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

--
2.17.1
diff mbox series

Patch

diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index e3135bb75f..716f9c1c7e 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -593,10 +593,15 @@  static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
 	pp->cmd_tbl_sg =
 			(struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);

-	writel_with_flush((unsigned long)pp->cmd_slot,
-			  port_mmio + PORT_LST_ADDR);
+	writel_with_flush((u32)pp->cmd_slot, port_mmio + PORT_LST_ADDR);
+#ifndef CONFIG_PHYS_64BIT
+	writel_with_flush(0, port_mmio + PORT_LST_ADDR_HI);
+#endif

 	writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
+#ifndef CONFIG_PHYS_64BIT
+	writel_with_flush(0, port_mmio + PORT_FIS_ADDR_HI);
+#endif

 #ifdef CONFIG_SUNXI_AHCI
 	sunxi_dma_init(port_mmio);