| Message ID | 20190709092814.21363-7-uboot@andestech.com |
|---|---|
| State | Superseded |
| Delegated to: | Andes |
| Headers | show |
| Series | Support Andes RISC-V l2cache on AE350 platform | expand |
On Tue, Jul 9, 2019 at 5:34 PM Andes <uboot@andestech.com> wrote: > > From: Rick Chen <rick@andestech.com> > > When L2 node exists inside cpus node, uclass_get_device > can not parse L2 node successfully. So move it outside > from cpus node. > > Also add tag-ram-ctl and data-ram-ctl attributes for > v5l2 cache controller driver. This can adjust timing > by requirement from dtb to improve performance. > > Signed-off-by: Rick Chen <rick@andestech.com> > Cc: Greentime Hu <greentime@andestech.com> > Cc: KC Lin <kclin@andestech.com> > --- > arch/riscv/dts/ae350_32.dts | 17 +++++++++++------ > arch/riscv/dts/ae350_64.dts | 17 +++++++++++------ > 2 files changed, 22 insertions(+), 12 deletions(-) > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts index cb6ee13..97b7cee 100644 --- a/arch/riscv/dts/ae350_32.dts +++ b/arch/riscv/dts/ae350_32.dts @@ -62,13 +62,18 @@ compatible = "riscv,cpu-intc"; }; }; + }; - L2: l2-cache@e0500000 { - compatible = "cache"; - cache-level = <2>; - cache-size = <0x40000>; - reg = <0x0 0xe0500000 0x0 0x40000>; - }; + L2: l2-cache@e0500000 { + compatible = "v5l2cache"; + cache-level = <2>; + cache-size = <0x40000>; + reg = <0xe0500000 0x40000>; + andes,inst-prefetch = <3>; + andes,data-prefetch = <3>; + /* The value format is <XRAMOCTL XRAMICTL> */ + andes,tag-ram-ctl = <0 0>; + andes,data-ram-ctl = <0 0>; }; memory@0 { diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts index 705491a..d8f00f8 100644 --- a/arch/riscv/dts/ae350_64.dts +++ b/arch/riscv/dts/ae350_64.dts @@ -62,13 +62,18 @@ compatible = "riscv,cpu-intc"; }; }; + }; - L2: l2-cache@e0500000 { - compatible = "cache"; - cache-level = <2>; - cache-size = <0x40000>; - reg = <0x0 0xe0500000 0x0 0x40000>; - }; + L2: l2-cache@e0500000 { + compatible = "v5l2cache"; + cache-level = <2>; + cache-size = <0x40000>; + reg = <0x0 0xe0500000 0x0 0x40000>; + andes,inst-prefetch = <3>; + andes,data-prefetch = <3>; + /* The value format is <XRAMOCTL XRAMICTL> */ + andes,tag-ram-ctl = <0 0>; + andes,data-ram-ctl = <0 0>; }; memory@0 {