diff mbox series

[U-Boot,v2,5/7] riscv: cache: Flush L2 cache before jump to linux

Message ID 20190709092814.21363-6-uboot@andestech.com
State Superseded
Delegated to: Andes
Headers show
Series Support Andes RISC-V l2cache on AE350 platform | expand

Commit Message

Andes July 9, 2019, 9:28 a.m. UTC
From: Rick Chen <rick@andestech.com>

Flush and disable cache in cleanup_before_linux()
which will be called before jump to linux.

The sequence will be preferred as below:
L1 flush -> L1 disable -> L2 flush -> L2 disable

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Cc: KC Lin <kclin@andestech.com>
---
 arch/riscv/cpu/ax25/cpu.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

Comments

Bin Meng July 11, 2019, 4:20 a.m. UTC | #1
On Tue, Jul 9, 2019 at 5:34 PM Andes <uboot@andestech.com> wrote:
>
> From: Rick Chen <rick@andestech.com>
>
> Flush and disable cache in cleanup_before_linux()
> which will be called before jump to linux.
>
> The sequence will be preferred as below:
> L1 flush -> L1 disable -> L2 flush -> L2 disable
>
> Signed-off-by: Rick Chen <rick@andestech.com>
> Cc: Greentime Hu <greentime@andestech.com>
> Cc: KC Lin <kclin@andestech.com>
> ---
>  arch/riscv/cpu/ax25/cpu.c | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
>
> diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c
> index 76689b2..31a714e 100644
> --- a/arch/riscv/cpu/ax25/cpu.c
> +++ b/arch/riscv/cpu/ax25/cpu.c
> @@ -7,6 +7,29 @@
>  /* CPU specific code */
>  #include <common.h>
>  #include <asm/cache.h>
> +#include <dm.h>
> +#include <dm/uclass-internal.h>
> +#include <cache.h>
> +
> +void enable_v5l2(void)
> +{
> +       struct udevice *dev = NULL;
> +
> +       uclass_find_first_device(UCLASS_CACHE, &dev);
> +
> +       if (dev)
> +               cache_enable(dev);
> +}
> +
> +void disable_v5l2(void)
> +{
> +       struct udevice *dev = NULL;
> +
> +       uclass_find_first_device(UCLASS_CACHE, &dev);
> +
> +       if (dev)
> +               cache_disable(dev);
> +}
>
>  /*
>   * cleanup_before_linux() is called just before we call linux
> @@ -22,6 +45,9 @@ int cleanup_before_linux(void)
>         cache_flush();
>         icache_disable();
>         dcache_disable();
> +#ifdef CONFIG_RISCV_NDS_CACHE
> +       disable_v5l2();
> +#endif

Since dcache_disable() is a weak symbol, could you please move the
codes in disable_v5l2() to the AX25 specific implementation of
dcache_disable()?

Regards,
Bin
Rick Chen July 17, 2019, 7:24 a.m. UTC | #2
Hi Bin

>
> On Tue, Jul 9, 2019 at 5:34 PM Andes <uboot@andestech.com> wrote:
> >
> > From: Rick Chen <rick@andestech.com>
> >
> > Flush and disable cache in cleanup_before_linux()
> > which will be called before jump to linux.
> >
> > The sequence will be preferred as below:
> > L1 flush -> L1 disable -> L2 flush -> L2 disable
> >
> > Signed-off-by: Rick Chen <rick@andestech.com>
> > Cc: Greentime Hu <greentime@andestech.com>
> > Cc: KC Lin <kclin@andestech.com>
> > ---
> >  arch/riscv/cpu/ax25/cpu.c | 26 ++++++++++++++++++++++++++
> >  1 file changed, 26 insertions(+)
> >
> > diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c
> > index 76689b2..31a714e 100644
> > --- a/arch/riscv/cpu/ax25/cpu.c
> > +++ b/arch/riscv/cpu/ax25/cpu.c
> > @@ -7,6 +7,29 @@
> >  /* CPU specific code */
> >  #include <common.h>
> >  #include <asm/cache.h>
> > +#include <dm.h>
> > +#include <dm/uclass-internal.h>
> > +#include <cache.h>
> > +
> > +void enable_v5l2(void)
> > +{
> > +       struct udevice *dev = NULL;
> > +
> > +       uclass_find_first_device(UCLASS_CACHE, &dev);
> > +
> > +       if (dev)
> > +               cache_enable(dev);
> > +}
> > +
> > +void disable_v5l2(void)
> > +{
> > +       struct udevice *dev = NULL;
> > +
> > +       uclass_find_first_device(UCLASS_CACHE, &dev);
> > +
> > +       if (dev)
> > +               cache_disable(dev);
> > +}
> >
> >  /*
> >   * cleanup_before_linux() is called just before we call linux
> > @@ -22,6 +45,9 @@ int cleanup_before_linux(void)
> >         cache_flush();
> >         icache_disable();
> >         dcache_disable();
> > +#ifdef CONFIG_RISCV_NDS_CACHE
> > +       disable_v5l2();
> > +#endif
>
> Since dcache_disable() is a weak symbol, could you please move the
> codes in disable_v5l2() to the AX25 specific implementation of
> dcache_disable()?
>

OK.
I will the codes in disable_v5l2() into dcache_disable().

Thanks
Rick

> Regards,
> Bin
diff mbox series

Patch

diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c
index 76689b2..31a714e 100644
--- a/arch/riscv/cpu/ax25/cpu.c
+++ b/arch/riscv/cpu/ax25/cpu.c
@@ -7,6 +7,29 @@ 
 /* CPU specific code */
 #include <common.h>
 #include <asm/cache.h>
+#include <dm.h>
+#include <dm/uclass-internal.h>
+#include <cache.h>
+
+void enable_v5l2(void)
+{
+	struct udevice *dev = NULL;
+
+	uclass_find_first_device(UCLASS_CACHE, &dev);
+
+	if (dev)
+		cache_enable(dev);
+}
+
+void disable_v5l2(void)
+{
+	struct udevice *dev = NULL;
+
+	uclass_find_first_device(UCLASS_CACHE, &dev);
+
+	if (dev)
+		cache_disable(dev);
+}
 
 /*
  * cleanup_before_linux() is called just before we call linux
@@ -22,6 +45,9 @@  int cleanup_before_linux(void)
 	cache_flush();
 	icache_disable();
 	dcache_disable();
+#ifdef CONFIG_RISCV_NDS_CACHE
+	disable_v5l2();
+#endif
 
 	return 0;
 }