| Message ID | 20190709092814.21363-5-uboot@andestech.com |
|---|---|
| State | Superseded |
| Delegated to: | Andes |
| Headers | show |
| Series | Support Andes RISC-V l2cache on AE350 platform | expand |
On Tue, Jul 9, 2019 at 5:34 PM Andes <uboot@andestech.com> wrote: > > From: Rick Chen <rick@andestech.com> > > Select the v5l2 UCLASS_CACHE driver for ax25. > > Signed-off-by: Rick Chen <rick@andestech.com> > Cc: Greentime Hu <greentime@andestech.com> > Cc: KC Lin <kclin@andestech.com> > --- > arch/riscv/cpu/ax25/Kconfig | 1 + > 1 file changed, 1 insertion(+) > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig index 6b4b92e..49be775 100644 --- a/arch/riscv/cpu/ax25/Kconfig +++ b/arch/riscv/cpu/ax25/Kconfig @@ -4,6 +4,7 @@ config RISCV_NDS imply CPU imply CPU_RISCV imply RISCV_TIMER + imply V5L2_CACHE imply ANDES_PLIC if RISCV_MMODE imply ANDES_PLMT if RISCV_MMODE help