From patchwork Tue Jul 2 08:32:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 1126060 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=socionext.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=nifty.com header.i=@nifty.com header.b="TOemes4z"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45dHhL6TNDz9sLt for ; Tue, 2 Jul 2019 18:38:42 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 965E5C21D56; Tue, 2 Jul 2019 08:36:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 85EDCC21E0F; Tue, 2 Jul 2019 08:33:43 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4F83EC21E18; Tue, 2 Jul 2019 08:33:13 +0000 (UTC) Received: from conuserg-08.nifty.com (conuserg-08.nifty.com [210.131.2.75]) by lists.denx.de (Postfix) with ESMTPS id D1600C21DD4 for ; Tue, 2 Jul 2019 08:33:07 +0000 (UTC) Received: from localhost.localdomain (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-08.nifty.com with ESMTP id x628Wdx3022428; Tue, 2 Jul 2019 17:32:45 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-08.nifty.com x628Wdx3022428 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1562056365; bh=MKckhxuUPom3jHnHL+5jxLn7iF5YYOgX3TP6oyXGm4I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TOemes4zHHqCrKAiNPQq8ylKNBFyBmNP2M0FSFyt6zzwAVsdGW8x1AaaOaixHHAzD vXxoOFvNjDG2Td8RU8QC4qxcF26rG/VI0+7urLApXEymtBd4eWhgGnbanIKyTuB0Md vT81mmb23ITMDueBxkihw+PVAwNjEw+wqrFv5TfDt4/C+Jly8qGx39x8iINhZemnzm ksXqAEC10QZ3GwTdNMd49WnyffynxESlREPPFeORcerN4P540+joFHwxVEfzD24wv3 1fVBItnhly903uYUz5ZEZtwvoWmeynidlJZBy//08YGawhtFG6jp9358g6lnI3B4E8 iTVcfkrH1MSIg== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Tue, 2 Jul 2019 17:32:22 +0900 Message-Id: <20190702083228.16882-12-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190702083228.16882-1-yamada.masahiro@socionext.com> References: <20190702083228.16882-1-yamada.masahiro@socionext.com> Cc: Tom Rini Subject: [U-Boot] [PATCH 12/18] ARM: uniphier: de-couple SG macros into base address and offset X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The SG_* macros represent the address of SoC-glue registers. For a planned new SoC, its base address will be changed. Turn the SG_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/arm32/debug_ll.S | 16 +++++------ .../boot-device/boot-device-ld11.c | 4 +-- .../boot-device/boot-device-pxs2.c | 2 +- .../boot-device/boot-device-pxs3.c | 2 +- .../mach-uniphier/boot-device/boot-device.c | 6 ++-- arch/arm/mach-uniphier/clk/clk-ld11.c | 14 +++++----- arch/arm/mach-uniphier/clk/pll-ld4.c | 4 +-- arch/arm/mach-uniphier/clk/pll-pro4.c | 2 +- .../debug-uart/debug-uart-pro4.c | 2 +- .../debug-uart/debug-uart-pro5.c | 2 +- .../arm/mach-uniphier/debug-uart/debug-uart.c | 5 ++-- arch/arm/mach-uniphier/dram_init.c | 2 +- arch/arm/mach-uniphier/memconf.c | 2 +- arch/arm/mach-uniphier/sg-regs.h | 28 +++++++++++-------- arch/arm/mach-uniphier/soc-info.c | 2 +- 15 files changed, 49 insertions(+), 44 deletions(-) diff --git a/arch/arm/mach-uniphier/arm32/debug_ll.S b/arch/arm/mach-uniphier/arm32/debug_ll.S index e56e1f679ca8..c155246ae8c9 100644 --- a/arch/arm/mach-uniphier/arm32/debug_ll.S +++ b/arch/arm/mach-uniphier/arm32/debug_ll.S @@ -22,7 +22,7 @@ #define DIV_ROUND(x, d) (((x) + ((d) / 2)) / (d)) .macro sg_set_pinsel, pin, muxval, mux_bits, reg_stride, ra, rd - ldr \ra, =(SG_PINCTRL_BASE + \pin * \mux_bits / 32 * \reg_stride) + ldr \ra, =(SG_BASE + SG_PINCTRL_BASE + \pin * \mux_bits / 32 * \reg_stride) ldr \rd, [\ra] and \rd, \rd, #~(((1 << \mux_bits) - 1) << (\pin * \mux_bits % 32)) orr \rd, \rd, #(\muxval << (\pin * \mux_bits % 32)) @@ -30,7 +30,7 @@ .endm ENTRY(debug_ll_init) - ldr r0, =SG_REVISION + ldr r0, =(SG_BASE + SG_REVISION) ldr r1, [r0] and r1, r1, #SG_REVISION_TYPE_MASK mov r1, r1, lsr #SG_REVISION_TYPE_SHIFT @@ -40,7 +40,7 @@ ENTRY(debug_ll_init) cmp r1, #0x26 bne ld4_end - ldr r0, =SG_IECTRL + ldr r0, =(SG_BASE + SG_IECTRL) ldr r1, [r0] orr r1, r1, #1 str r1, [r0] @@ -59,7 +59,7 @@ ld4_end: sg_set_pinsel 128, 0, 4, 8, r0, r1 @ TXD0 -> TXD0 - ldr r0, =SG_LOADPINCTRL + ldr r0, =(SG_BASE + SG_LOADPINCTRL) mov r1, #1 str r1, [r0] @@ -78,7 +78,7 @@ pro4_end: cmp r1, #0x29 bne sld8_end - ldr r0, =SG_IECTRL + ldr r0, =(SG_BASE + SG_IECTRL) ldr r1, [r0] orr r1, r1, #1 str r1, [r0] @@ -100,7 +100,7 @@ sld8_end: sg_set_pinsel 51, 0, 4, 8, r0, r1 @ TXD2 -> TXD2 sg_set_pinsel 53, 0, 4, 8, r0, r1 @ TXD3 -> TXD3 - ldr r0, =SG_LOADPINCTRL + ldr r0, =(SG_BASE + SG_LOADPINCTRL) mov r1, #1 str r1, [r0] @@ -119,7 +119,7 @@ pro5_end: cmp r1, #0x2E bne pxs2_end - ldr r0, =SG_IECTRL + ldr r0, =(SG_BASE + SG_IECTRL) ldr r1, [r0] orr r1, r1, #1 str r1, [r0] @@ -144,7 +144,7 @@ pxs2_end: cmp r1, #0x2F bne ld6b_end - ldr r0, =SG_IECTRL + ldr r0, =(SG_BASE + SG_IECTRL) ldr r1, [r0] orr r1, r1, #1 str r1, [r0] diff --git a/arch/arm/mach-uniphier/boot-device/boot-device-ld11.c b/arch/arm/mach-uniphier/boot-device/boot-device-ld11.c index 67650e0ae332..2a8238e5a6e4 100644 --- a/arch/arm/mach-uniphier/boot-device/boot-device-ld11.c +++ b/arch/arm/mach-uniphier/boot-device/boot-device-ld11.c @@ -52,10 +52,10 @@ const unsigned uniphier_ld11_boot_device_count = int uniphier_ld11_boot_device_is_usb(void) { - return !!(~readl(SG_PINMON0) & 0x00000080); + return !!(~readl(sg_base + SG_PINMON0) & 0x00000080); } int uniphier_ld20_boot_device_is_usb(void) { - return !!(~readl(SG_PINMON0) & 0x00000780); + return !!(~readl(sg_base + SG_PINMON0) & 0x00000780); } diff --git a/arch/arm/mach-uniphier/boot-device/boot-device-pxs2.c b/arch/arm/mach-uniphier/boot-device/boot-device-pxs2.c index f032664a0f34..0d7658424192 100644 --- a/arch/arm/mach-uniphier/boot-device/boot-device-pxs2.c +++ b/arch/arm/mach-uniphier/boot-device/boot-device-pxs2.c @@ -52,7 +52,7 @@ const unsigned uniphier_pxs2_boot_device_count = int uniphier_pxs2_boot_device_is_usb(void) { - return !!(readl(SG_PINMON0) & 0x00000040); + return !!(readl(sg_base + SG_PINMON0) & 0x00000040); } unsigned int uniphier_pxs2_boot_device_fixup(unsigned int mode) diff --git a/arch/arm/mach-uniphier/boot-device/boot-device-pxs3.c b/arch/arm/mach-uniphier/boot-device/boot-device-pxs3.c index 8de3737b2881..0ed9ab281236 100644 --- a/arch/arm/mach-uniphier/boot-device/boot-device-pxs3.c +++ b/arch/arm/mach-uniphier/boot-device/boot-device-pxs3.c @@ -36,5 +36,5 @@ const unsigned uniphier_pxs3_boot_device_count = int uniphier_pxs3_boot_device_is_usb(void) { - return !!(readl(SG_PINMON2) & BIT(31)); + return !!(readl(sg_base + SG_PINMON2) & BIT(31)); } diff --git a/arch/arm/mach-uniphier/boot-device/boot-device.c b/arch/arm/mach-uniphier/boot-device/boot-device.c index b0b39d8e02d4..420e0ba722c4 100644 --- a/arch/arm/mach-uniphier/boot-device/boot-device.c +++ b/arch/arm/mach-uniphier/boot-device/boot-device.c @@ -144,7 +144,7 @@ static unsigned int __uniphier_boot_device_raw( if (info->boot_device_is_usb && info->boot_device_is_usb()) return BOOT_DEVICE_USB; - boot_sel = readl(SG_PINMON0) >> info->boot_device_sel_shift; + boot_sel = readl(sg_base + SG_PINMON0) >> info->boot_device_sel_shift; BUG_ON(!is_power_of_2(*info->boot_device_count)); boot_sel &= *info->boot_device_count - 1; @@ -197,7 +197,7 @@ int uniphier_have_internal_stm(void) int uniphier_boot_from_backend(void) { - return !!(readl(SG_PINMON0) & BIT(27)); + return !!(readl(sg_base + SG_PINMON0) & BIT(27)); } #ifndef CONFIG_SPL_BUILD @@ -232,7 +232,7 @@ static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) boot_device_count = *info->boot_device_count; - boot_sel = readl(SG_PINMON0) >> info->boot_device_sel_shift; + boot_sel = readl(sg_base + SG_PINMON0) >> info->boot_device_sel_shift; boot_sel &= boot_device_count - 1; printf("\nBoot Mode Sel:\n"); diff --git a/arch/arm/mach-uniphier/clk/clk-ld11.c b/arch/arm/mach-uniphier/clk/clk-ld11.c index e997acf1b7d7..0917b33c2546 100644 --- a/arch/arm/mach-uniphier/clk/clk-ld11.c +++ b/arch/arm/mach-uniphier/clk/clk-ld11.c @@ -17,16 +17,16 @@ void uniphier_ld11_clk_init(void) { /* if booted from a device other than USB, without stand-by MPU */ - if ((readl(SG_PINMON0) & BIT(27)) && + if ((readl(sg_base + SG_PINMON0) & BIT(27)) && uniphier_boot_device_raw() != BOOT_DEVICE_USB) { - writel(1, SG_ETPHYPSHUT); - writel(1, SG_ETPHYCNT); + writel(1, sg_base + SG_ETPHYPSHUT); + writel(1, sg_base + SG_ETPHYCNT); udelay(1); /* wait for regulator level 1.1V -> 2.5V */ - writel(3, SG_ETPHYCNT); - writel(3, SG_ETPHYPSHUT); - writel(7, SG_ETPHYCNT); + writel(3, sg_base + SG_ETPHYCNT); + writel(3, sg_base + SG_ETPHYPSHUT); + writel(7, sg_base + SG_ETPHYCNT); } /* TODO: use "mmc-pwrseq-emmc" */ @@ -37,7 +37,7 @@ void uniphier_ld11_clk_init(void) int ch; for (ch = 0; ch < 3; ch++) { - void __iomem *phyctrl = (void __iomem *)SG_USBPHYCTRL; + void __iomem *phyctrl = sg_base + SG_USBPHYCTRL; writel(0x82280600, phyctrl + 8 * ch); writel(0x00000106, phyctrl + 8 * ch + 4); diff --git a/arch/arm/mach-uniphier/clk/pll-ld4.c b/arch/arm/mach-uniphier/clk/pll-ld4.c index 6a145a3baa12..34f1c9cc2898 100644 --- a/arch/arm/mach-uniphier/clk/pll-ld4.c +++ b/arch/arm/mach-uniphier/clk/pll-ld4.c @@ -16,7 +16,7 @@ static void upll_init(void) { u32 tmp, clk_mode_upll, clk_mode_axosel; - tmp = readl(SG_PINMON0); + tmp = readl(sg_base + SG_PINMON0); clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK; clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; @@ -56,7 +56,7 @@ static void vpll_init(void) { u32 tmp, clk_mode_axosel; - tmp = readl(SG_PINMON0); + tmp = readl(sg_base + SG_PINMON0); clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; /* set 1 to VPLA27WP and VPLA27WP */ diff --git a/arch/arm/mach-uniphier/clk/pll-pro4.c b/arch/arm/mach-uniphier/clk/pll-pro4.c index 2ee2ed6bd662..312a5fcfdfcf 100644 --- a/arch/arm/mach-uniphier/clk/pll-pro4.c +++ b/arch/arm/mach-uniphier/clk/pll-pro4.c @@ -17,7 +17,7 @@ static void vpll_init(void) u32 tmp, clk_mode_axosel; /* Set VPLL27A & VPLL27B */ - tmp = readl(SG_PINMON0); + tmp = readl(sg_base + SG_PINMON0); clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */ diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart-pro4.c b/arch/arm/mach-uniphier/debug-uart/debug-uart-pro4.c index 0d6629918acc..9017a24a1049 100644 --- a/arch/arm/mach-uniphier/debug-uart/debug-uart-pro4.c +++ b/arch/arm/mach-uniphier/debug-uart/debug-uart-pro4.c @@ -20,7 +20,7 @@ unsigned int uniphier_pro4_debug_uart_init(void) sg_set_iectrl(0); sg_set_pinsel(128, 0, 4, 8); /* TXD0 -> TXD0 */ - writel(1, SG_LOADPINCTRL); + writel(1, sg_base + SG_LOADPINCTRL); tmp = readl(SC_CLKCTRL); tmp |= SC_CLKCTRL_CEN_PERI; diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart-pro5.c b/arch/arm/mach-uniphier/debug-uart/debug-uart-pro5.c index 1a0a942f2dca..8e4d15c2913e 100644 --- a/arch/arm/mach-uniphier/debug-uart/debug-uart-pro5.c +++ b/arch/arm/mach-uniphier/debug-uart/debug-uart-pro5.c @@ -23,7 +23,7 @@ unsigned int uniphier_pro5_debug_uart_init(void) sg_set_pinsel(51, 0, 4, 8); /* TXD2 -> TXD2 */ sg_set_pinsel(53, 0, 4, 8); /* TXD3 -> TXD3 */ - writel(1, SG_LOADPINCTRL); + writel(1, sg_base + SG_LOADPINCTRL); tmp = readl(SC_CLKCTRL); tmp |= SC_CLKCTRL_CEN_PERI; diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart.c b/arch/arm/mach-uniphier/debug-uart/debug-uart.c index bc96b2e7be1f..a70ce59accdc 100644 --- a/arch/arm/mach-uniphier/debug-uart/debug-uart.c +++ b/arch/arm/mach-uniphier/debug-uart/debug-uart.c @@ -32,7 +32,8 @@ void sg_set_pinsel(unsigned int pin, unsigned int muxval, unsigned int mux_bits, unsigned int reg_stride) { unsigned int shift = pin * mux_bits % 32; - unsigned long reg = SG_PINCTRL_BASE + pin * mux_bits / 32 * reg_stride; + void __iomem *reg = sg_base + SG_PINCTRL_BASE + + pin * mux_bits / 32 * reg_stride; u32 mask = (1U << mux_bits) - 1; u32 tmp; @@ -45,7 +46,7 @@ void sg_set_pinsel(unsigned int pin, unsigned int muxval, void sg_set_iectrl(unsigned int pin) { unsigned int bit = pin % 32; - unsigned long reg = SG_IECTRL + pin / 32 * 4; + void __iomem *reg = sg_base + SG_IECTRL + pin / 32 * 4; u32 tmp; tmp = readl(reg); diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index fa4b3e386b83..eca340b094e6 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -85,7 +85,7 @@ static int uniphier_memconf_decode(struct uniphier_dram_map *dram_map) return -EINVAL; } - val = readl(SG_MEMCONF); + val = readl(sg_base + SG_MEMCONF); /* set up ch0 */ dram_map[0].base = CONFIG_SYS_SDRAM_BASE; diff --git a/arch/arm/mach-uniphier/memconf.c b/arch/arm/mach-uniphier/memconf.c index 8105368df147..f69b489b76e5 100644 --- a/arch/arm/mach-uniphier/memconf.c +++ b/arch/arm/mach-uniphier/memconf.c @@ -140,7 +140,7 @@ static int __uniphier_memconf_init(const struct uniphier_board_data *bd, } out: - writel(val, SG_MEMCONF); + writel(val, sg_base + SG_MEMCONF); return 0; } diff --git a/arch/arm/mach-uniphier/sg-regs.h b/arch/arm/mach-uniphier/sg-regs.h index 39ffed5885df..cba02d1f4aee 100644 --- a/arch/arm/mach-uniphier/sg-regs.h +++ b/arch/arm/mach-uniphier/sg-regs.h @@ -10,15 +10,19 @@ #ifndef UNIPHIER_SG_REGS_H #define UNIPHIER_SG_REGS_H +#ifndef __ASSEMBLY__ +#include +#define sg_base ((void __iomem *)SG_BASE) +#endif + /* Base Address */ -#define SG_CTRL_BASE 0x5f800000 -#define SG_DBG_BASE 0x5f900000 +#define SG_BASE 0x5f800000 /* Revision */ -#define SG_REVISION (SG_CTRL_BASE | 0x0000) +#define SG_REVISION 0x0000 /* Memory Configuration */ -#define SG_MEMCONF (SG_CTRL_BASE | 0x0400) +#define SG_MEMCONF 0x0400 #define SG_MEMCONF_CH0_SZ_MASK ((0x1 << 10) | (0x03 << 0)) #define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0)) @@ -54,22 +58,22 @@ #define SG_MEMCONF_SPARSEMEM (0x1 << 4) -#define SG_USBPHYCTRL (SG_CTRL_BASE | 0x500) -#define SG_ETPHYPSHUT (SG_CTRL_BASE | 0x554) -#define SG_ETPHYCNT (SG_CTRL_BASE | 0x550) +#define SG_USBPHYCTRL 0x0500 +#define SG_ETPHYPSHUT 0x0554 +#define SG_ETPHYCNT 0x0550 /* Pin Control */ -#define SG_PINCTRL_BASE (SG_CTRL_BASE | 0x1000) +#define SG_PINCTRL_BASE 0x1000 /* PH1-Pro4, PH1-Pro5 */ -#define SG_LOADPINCTRL (SG_CTRL_BASE | 0x1700) +#define SG_LOADPINCTRL 0x1700 /* Input Enable */ -#define SG_IECTRL (SG_CTRL_BASE | 0x1d00) +#define SG_IECTRL 0x1d00 /* Pin Monitor */ -#define SG_PINMON0 (SG_DBG_BASE | 0x0100) -#define SG_PINMON2 (SG_DBG_BASE | 0x0108) +#define SG_PINMON0 0x00100100 +#define SG_PINMON2 0x00100108 #define SG_PINMON0_CLK_MODE_UPLLSRC_MASK (0x3 << 19) #define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT (0x0 << 19) diff --git a/arch/arm/mach-uniphier/soc-info.c b/arch/arm/mach-uniphier/soc-info.c index ce2d4b6dea4c..f021a8cab330 100644 --- a/arch/arm/mach-uniphier/soc-info.c +++ b/arch/arm/mach-uniphier/soc-info.c @@ -13,7 +13,7 @@ static unsigned int __uniphier_get_revision_field(unsigned int mask, unsigned int shift) { - u32 revision = readl(SG_REVISION); + u32 revision = readl(sg_base + SG_REVISION); return (revision >> shift) & mask; }