From patchwork Tue Jun 11 14:51:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1113997 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="kCyPcKSr"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45NYxp4gypz9s5c for ; Wed, 12 Jun 2019 01:36:14 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 32C2EC221B5; Tue, 11 Jun 2019 15:12:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 094BFC22116; Tue, 11 Jun 2019 15:10:18 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 3305BC220D3; Tue, 11 Jun 2019 14:57:47 +0000 (UTC) Received: from mail-pl1-f194.google.com (mail-pl1-f194.google.com [209.85.214.194]) by lists.denx.de (Postfix) with ESMTPS id 71674C21EA8 for ; Tue, 11 Jun 2019 14:57:43 +0000 (UTC) Received: by mail-pl1-f194.google.com with SMTP id go2so5220036plb.9 for ; Tue, 11 Jun 2019 07:57:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EGZ8QbOC3Lmpsm4GK+xadppvBx7oC2rPSb4ZO01EuV4=; b=kCyPcKSrZoiLK8CVxFaI7Rm7zyQ8KlBV2F6SNvLdxg9EgHHGQL6daqv2k045FwuuTL JzwFXKj1KZETEoCzkT4hGf41E2165xGDDRHXfSsbBYSvuR2RB/987A/OITaW5deVEV6g eOsLIE1mKwvXY56nAxB4Jwmgvjy6Mt+wdNfRY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EGZ8QbOC3Lmpsm4GK+xadppvBx7oC2rPSb4ZO01EuV4=; b=MuQzoKb1wsRCOTNdvgdJ3Z3lbNoJ3G29lYYylEsPm7m9cj7acTwgDBM/QleLECAvQs xEHjb5EXtDyM5LnHXOpqZQzgL9KsyyWLqonIGptDbgK4zr1U3BwmDLpvqLF+UvIG2dwO K+y0SCu5xX41k4mKprreN2JiGCPFwcq/zG9BjaDp0NV9PRLIKbUTcm5qtRm7a6b/DuQu DT3QEnEJ0w5eO2HjktsCcAiyq3Ab6ouOm6FCJiHegp6kKVbwyRVTaZFuUqC0x4hNQc3I PzJ7Ao36ohOsiYiIOcWJpRE3EwEM00kRIe0kTNFzNa6qG5S2/+Onu7H8YezT0mDjdBfx 0grg== X-Gm-Message-State: APjAAAUEjZtCUUCKVkrfJONTYdogIY7IPRbtKM8/96T2bN8jTAPDnIhU 5av5l7XyAln8kMhd+xyKoIfnNUmpQ0g= X-Google-Smtp-Source: APXvYqxsU7m4qXL9HkubW2kPt53rrjtgE7E8G/DY28wODex3aiB59IrUuvxtXTG7Wi74iCJk8bJOyA== X-Received: by 2002:a17:902:522:: with SMTP id 31mr72398477plf.296.1560265062043; Tue, 11 Jun 2019 07:57:42 -0700 (PDT) Received: from localhost.localdomain ([115.97.180.18]) by smtp.gmail.com with ESMTPSA id e9sm16206208pfn.154.2019.06.11.07.57.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Jun 2019 07:57:41 -0700 (PDT) From: Jagan Teki To: Simon Glass , Philipp Tomsich , Kever Yang , YouMin Chen , u-boot@lists.denx.de Date: Tue, 11 Jun 2019 20:21:32 +0530 Message-Id: <20190611145135.21399-90-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190611145135.21399-1-jagan@amarulasolutions.com> References: <20190611145135.21399-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Cc: linux-rockchip@lists.infradead.org, linux-amarula@amarulasolutions.com, gajjar04akash@gmail.com Subject: [U-Boot] [PATCH 89/92] ram: rk3399: Set lpddr4 MR14 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Set MR14 based identified controller in lpddr4 as part of LPDDR set rate initialization phase. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen --- drivers/ram/rockchip/sdram_rk3399.c | 50 +++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 38fc8ffe63..859f26462d 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -2045,6 +2045,55 @@ static void set_lpddr4_MR12(const struct chan_info *chan, } } +static void set_lpddr4_MR14(const struct chan_info *chan, + struct rk3399_sdram_params *params, u32 ctl, + bool ctl_phy_reg, u32 mr5) +{ + u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg); + u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg); + struct io_setting *io; + u32 reg_value; + + io = lpddr4_get_io_settings(params, mr5); + + reg_value = io->dq_vref; + + switch (ctl) { + case 0: + clrsetbits_le32(&denali_ctl[142], 0xFFFF << 16, + reg_value << 16); + clrsetbits_le32(&denali_ctl[156], 0xFFFF << 16, + reg_value << 16); + + clrsetbits_le32(&denali_pi[132], 0xFF << 16, reg_value << 16); + clrsetbits_le32(&denali_pi[140], 0xFF << 0, reg_value << 0); + clrsetbits_le32(&denali_pi[147], 0xFF << 16, reg_value << 16); + clrsetbits_le32(&denali_pi[155], 0xFF << 0, reg_value << 0); + break; + case 1: + clrsetbits_le32(&denali_ctl[143], 0xFFFF, reg_value); + clrsetbits_le32(&denali_ctl[157], 0xFFFF, reg_value); + + clrsetbits_le32(&denali_pi[130], 0xFF << 0, reg_value << 0); + clrsetbits_le32(&denali_pi[137], 0xFF << 16, reg_value << 16); + clrsetbits_le32(&denali_pi[145], 0xFF << 0, reg_value << 0); + clrsetbits_le32(&denali_pi[152], 0xFF << 16, reg_value << 16); + break; + case 2: + default: + clrsetbits_le32(&denali_ctl[143], 0xFFFF << 16, + reg_value << 16); + clrsetbits_le32(&denali_ctl[157], 0xFFFF << 16, + reg_value << 16); + + clrsetbits_le32(&denali_pi[127], 0xFF << 16, reg_value << 16); + clrsetbits_le32(&denali_pi[135], 0xFF << 0, reg_value << 0); + clrsetbits_le32(&denali_pi[142], 0xFF << 16, reg_value << 16); + clrsetbits_le32(&denali_pi[150], 0xFF << 0, reg_value << 0); + break; + } +} + static void lpddr4_copy_phy(struct dram_info *dram, struct rk3399_sdram_params *params, u32 phy, struct rk3399_sdram_params *timings, @@ -2295,6 +2344,7 @@ static void lpddr4_copy_phy(struct dram_info *dram, set_lpddr4_ca_odt(&dram->chan[channel], timings, ctl, true, true, mr5); set_lpddr4_MR3(&dram->chan[channel], timings, ctl, true, mr5); set_lpddr4_MR12(&dram->chan[channel], timings, ctl, true, mr5); + set_lpddr4_MR14(&dram->chan[channel], timings, ctl, true, mr5); /* * if phy_sw_master_mode_X not bypass mode,