From patchwork Tue Jun 11 14:51:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1114013 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="mKVBpxMz"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45NZ602WnZz9sBp for ; Wed, 12 Jun 2019 01:43:20 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 03E58C22215; Tue, 11 Jun 2019 15:13:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D4C90C22101; Tue, 11 Jun 2019 15:13:06 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 806F7C21CB6; Tue, 11 Jun 2019 14:56:25 +0000 (UTC) Received: from mail-pg1-f195.google.com (mail-pg1-f195.google.com [209.85.215.195]) by lists.denx.de (Postfix) with ESMTPS id 60FAAC220AC for ; Tue, 11 Jun 2019 14:56:22 +0000 (UTC) Received: by mail-pg1-f195.google.com with SMTP id p10so1268500pgn.1 for ; Tue, 11 Jun 2019 07:56:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GsHylnIB++iBMUiXDFzXoSlZ07F6iOqo9v8tqN3hKF8=; b=mKVBpxMzIJFKeWZK+c3fX7LfTBS7Ymwsxe/GQ62IbsJ+jkJr+gUjxIEQNRCCxFuogz mdqKBq4uxk//yL0aFgVUcYdoXz2bZq7pfFk5U6NgmMpNScc1u9E5c/dlI2a0iXVOuuGM D7dIN0QqTXMO0napXMir9SEXGjkjxEEFLmNzU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GsHylnIB++iBMUiXDFzXoSlZ07F6iOqo9v8tqN3hKF8=; b=toaB8Pnf0GyyzQ0cVRmCtfZEh2JFd5iOSpLTrShvJ6moLa4iBfwSVdoisLXeR02bUt 9njkeoa0UmwuHLuLYQFrknksHmAJ/onbYYalOtPemww9lm1frjpz3ws4+bm7C/Z3QMzE zaY7iJNYvRsMJXMl/mJo/ql1G5u83ZR00ZxXjCI0RlUrZs0nuS//eduJ80BM9NdofUf5 1tZIOTVkVXJUUH7FVZuyUqBhHFyTIJi3rQGDOvNWu04E4YCf5YxLm+HZhfH4dvRj33z+ 0ynw34VIKEBgqV1lWrmkrEDLJjyLmXBdOZtL3iZvd8XL7v5GH+AhAHbRyFdOiDsbseza ERlw== X-Gm-Message-State: APjAAAU3gfkvUoCAeitmsplJYtJ9rBGmmTWnf5aiI21dK2d5d3yLyjkW aRoXCpo+8Nk6AN2ZzQ18xCzRhQ== X-Google-Smtp-Source: APXvYqxJ3qRbNGLC3BkbsgUkru7+UzBJlMH7t4bRylg74YhbDeWjIPxRHBXZYBnkZtFVaGD7fOFR4w== X-Received: by 2002:a63:6c87:: with SMTP id h129mr21163121pgc.427.1560264980824; Tue, 11 Jun 2019 07:56:20 -0700 (PDT) Received: from localhost.localdomain ([115.97.180.18]) by smtp.gmail.com with ESMTPSA id e9sm16206208pfn.154.2019.06.11.07.56.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Jun 2019 07:56:20 -0700 (PDT) From: Jagan Teki To: Simon Glass , Philipp Tomsich , Kever Yang , YouMin Chen , u-boot@lists.denx.de Date: Tue, 11 Jun 2019 20:21:11 +0530 Message-Id: <20190611145135.21399-69-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190611145135.21399-1-jagan@amarulasolutions.com> References: <20190611145135.21399-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Cc: linux-rockchip@lists.infradead.org, linux-amarula@amarulasolutions.com, gajjar04akash@gmail.com Subject: [U-Boot] [PATCH 68/92] ram: rk3399: Configure tsel write ca for lpddr4 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" tsel write ca_p and ca_n values need to write on PHY 544, 672 and 800 to configure ds odt. Configure the same PHY register for lpddr4 would require a mask value of (300 << 8). Add support for it. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen --- drivers/ram/rockchip/sdram_rk3399.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index ecc215b9c7..a251fc6045 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -503,9 +503,18 @@ static void set_ds_odt(const struct chan_info *chan, /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */ reg_value = tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 0x4); - clrsetbits_le32(&denali_phy[544], 0xff, reg_value); - clrsetbits_le32(&denali_phy[672], 0xff, reg_value); - clrsetbits_le32(&denali_phy[800], 0xff, reg_value); + if (sdram_params->base.dramtype == LPDDR4) { + /* LPDDR4 these register read always return 0, so + * can not use clrsetbits_le32(), need to write32 + */ + writel((0x300 << 8) | reg_value, &denali_phy[544]); + writel((0x300 << 8) | reg_value, &denali_phy[672]); + writel((0x300 << 8) | reg_value, &denali_phy[800]); + } else { + clrsetbits_le32(&denali_phy[544], 0xff, reg_value); + clrsetbits_le32(&denali_phy[672], 0xff, reg_value); + clrsetbits_le32(&denali_phy[800], 0xff, reg_value); + } /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */ clrsetbits_le32(&denali_phy[928], 0xff, reg_value);