From patchwork Tue Jun 11 14:50:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1113920 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="WnwtPCWu"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45NYJH46n8z9s5c for ; Wed, 12 Jun 2019 01:07:11 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 35BEFC2211B; Tue, 11 Jun 2019 15:02:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 03935C220FB; Tue, 11 Jun 2019 15:01:16 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C31F3C220E8; Tue, 11 Jun 2019 14:55:08 +0000 (UTC) Received: from mail-pg1-f194.google.com (mail-pg1-f194.google.com [209.85.215.194]) by lists.denx.de (Postfix) with ESMTPS id 7BDB8C220BA for ; Tue, 11 Jun 2019 14:55:04 +0000 (UTC) Received: by mail-pg1-f194.google.com with SMTP id f21so1099985pgi.3 for ; Tue, 11 Jun 2019 07:55:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=q9WmmKSiG6PRsHUFUAVRH5Oq8xmXKYOkeIJI7ZtLjSw=; b=WnwtPCWuW2aVi9Q5IUPjCASprnBKOhTDr/I4/CLqIeWw4j8Rp9143C4UYPEYs0w7De ssvei//y2TxkFlh5Myz45D8QnJ4PLV3aAzgeXB0Hrbk3kS4Hc+1meKUeg70BDAuRACcf pPKNMb6jTx2SdeNMpdrIMVb7+shRVMg16kDYQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=q9WmmKSiG6PRsHUFUAVRH5Oq8xmXKYOkeIJI7ZtLjSw=; b=pAQFV0YNLrfHX+0qiLz6lvohxpFgHSU8xQ+L3LKe4iKQvlpIMezkzT+0hEA9Vv8OH8 zNzCds2Gn8cnjayBeAYRjmkfLZKRx+dkwrk02IoBNytrV967Tx+LztGJS+haNhRoWxZA zU1LizNQjLo8kwaAUJJT8i+gjtCVdw7JEHfDDatC3tnymybIFLjOAeX7+A/OhDPXooa0 h/Sc6Fe1OHH/LR2S2SNtJ/paCHZJyuHVRbUCI0H0011bNgATqypI1vWmn60rJG/VigOf xgJAlQv9umDbL6p0gD06r2LOvTxLtZY4k3eytjxo/nHAAar/tOyfvW7ruZ/lV0/cHRRj jFrA== X-Gm-Message-State: APjAAAUxWygCBt4gS7vI4ZCSQW+hOcm1R/zsy82bW3xcGZdmuMMPeM+v ps6LcfXufijKL7pWR2rsZT8GCw== X-Google-Smtp-Source: APXvYqzWXgsJpGGFSwem1gWsd36L4j7JyMPkAZGRsQjQaZD7YLIftXRYEdRb9pb1ylpkZTGvCOuJ1Q== X-Received: by 2002:a17:90a:2430:: with SMTP id h45mr28194841pje.14.1560264903013; Tue, 11 Jun 2019 07:55:03 -0700 (PDT) Received: from localhost.localdomain ([115.97.180.18]) by smtp.gmail.com with ESMTPSA id e9sm16206208pfn.154.2019.06.11.07.54.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Jun 2019 07:55:02 -0700 (PDT) From: Jagan Teki To: Simon Glass , Philipp Tomsich , Kever Yang , YouMin Chen , u-boot@lists.denx.de Date: Tue, 11 Jun 2019 20:20:51 +0530 Message-Id: <20190611145135.21399-49-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190611145135.21399-1-jagan@amarulasolutions.com> References: <20190611145135.21399-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Cc: linux-rockchip@lists.infradead.org, linux-amarula@amarulasolutions.com, gajjar04akash@gmail.com Subject: [U-Boot] [PATCH 48/92] ram: rk3399: Compute stride for 2 channels X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" stride value from sdram timings can be computed dynamically based on the determined capacity for the given channel. Right now these stride values are taken as part of sdram timings via dtsi, but it possible to use same timings dtsi for given frequency even though the configured board sdram do support single channel with different size by dynamically detect the stride value. Example, NanoPi NEO4 do have DDR3-1866, but with single channel and 1GB size with dynamic stride detection it is possible to use existing rk3399-sdram-ddr3-1866.dtsi whose stride, number of channels and capacity it support is d efferent. So, add initial support to calculate the stride value for 2 channels sdram, which is available by default on existing boards. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen --- drivers/ram/rockchip/sdram_rk3399.c | 72 ++++++++++++++++++++++++++++- 1 file changed, 71 insertions(+), 1 deletion(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 1acf9efe9c..5985c37f08 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -1185,8 +1185,76 @@ static int switch_to_phy_index1(struct dram_info *dram, return 0; } +static unsigned char calculate_stride(struct rk3399_sdram_params *sdram_params) +{ + unsigned int stride = sdram_params->base.stride; + unsigned int channel, chinfo = 0; + unsigned int ch_cap[2] = {0, 0}; + u64 cap; + + for (channel = 0; channel < 2; channel++) { + unsigned int cs0_cap = 0; + unsigned int cs1_cap = 0; + struct sdram_cap_info *cap_info = + &sdram_params->ch[channel].cap_info; + + if (cap_info->col == 0) + continue; + + cs0_cap = (1 << (cap_info->cs0_row + cap_info->col + + cap_info->bk + cap_info->bw - 20)); + if (cap_info->rank > 1) + cs1_cap = cs0_cap >> (cap_info->cs0_row + - cap_info->cs1_row); + if (cap_info->row_3_4) { + cs0_cap = cs0_cap * 3 / 4; + cs1_cap = cs1_cap * 3 / 4; + } + ch_cap[channel] = cs0_cap + cs1_cap; + chinfo |= 1 << channel; + } + + /* stride calculation for 2 channels, default gstride type is 256B */ + if (ch_cap[0] == ch_cap[1]) { + cap = ch_cap[0] + ch_cap[1]; + switch (cap) { + /* 512MB */ + case 512: + stride = 0; + break; + /* 1GB */ + case 1024: + stride = 0x5; + break; + /* + * 768MB + 768MB same as total 2GB memory + * useful space: 0-768MB 1GB-1792MB + */ + case 1536: + /* 2GB */ + case 2048: + stride = 0x9; + break; + /* 1536MB + 1536MB */ + case 3072: + stride = 0x11; + break; + /* 4GB */ + case 4096: + stride = 0xD; + break; + default: + printf("%s: Unable to calculate stride for ", __func__); + print_size((cap * (1 << 20)), " capacity\n"); + break; + } + } + + return stride; +} + static int sdram_init(struct dram_info *dram, - const struct rk3399_sdram_params *sdram_params) + struct rk3399_sdram_params *sdram_params) { unsigned char dramtype = sdram_params->base.dramtype; unsigned int ddr_freq = sdram_params->base.ddr_freq; @@ -1235,6 +1303,8 @@ static int sdram_init(struct dram_info *dram, set_ddrconfig(chan, sdram_params, channel, sdram_params->ch[channel].cap_info.ddrconfig); } + + sdram_params->base.stride = calculate_stride(sdram_params); dram_all_config(dram, sdram_params); switch_to_phy_index1(dram, sdram_params);