From patchwork Tue Jun 11 14:50:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1113918 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="AQhq3ai+"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45NYH568Gtz9sCJ for ; Wed, 12 Jun 2019 01:06:09 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 685FFC2212C; Tue, 11 Jun 2019 14:56:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 5FCB0C21E4E; Tue, 11 Jun 2019 14:56:31 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A898DC220AC; Tue, 11 Jun 2019 14:54:24 +0000 (UTC) Received: from mail-pl1-f193.google.com (mail-pl1-f193.google.com [209.85.214.193]) by lists.denx.de (Postfix) with ESMTPS id B6E65C220CA for ; Tue, 11 Jun 2019 14:54:20 +0000 (UTC) Received: by mail-pl1-f193.google.com with SMTP id b7so188072pls.6 for ; Tue, 11 Jun 2019 07:54:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5Yf1E/nMMJ1uTpuqkdMMi/r9H01gEX8XKmpuGy2lGns=; b=AQhq3ai+Dfe1IeNOulTWAetQAgCv5y8U7E2g2NU1kpyvdH9bgTp1GRoqB0cOd8j7r5 dDzp963DwB8WdGVrUsy0qadwDNZUX3r4960pVu4FeBmdlThM6974xZPUrPZ7pKp0dU74 f+kz2QAc/yn0fhIHyxO7S3P41PHIb6ZxwopEs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5Yf1E/nMMJ1uTpuqkdMMi/r9H01gEX8XKmpuGy2lGns=; b=tbLEhJoEiyjPE0S7t7rjT/tG9Du780UEdB69tcJ+lkEUBUdm47E8osbhSHXB7zUYbO NTi2tsHCYYTp+BhOngHde8aAREOPBjlBa0XT/Kavo3k/beuM0b6FPnfwTBo/7eFm2WOZ 75556XefcUA6ghaOffit0UC62zKW2ZjVdBHwsl4PvQrqO9FWXs0Z2PE3zax8kmk0SkrR mjSxXonWzcm5TBfIB8M9FLYSpZUaNusZ3T7ksnmEYQ0z2FmTEsA5uJBQUShPX5W5EotP MRWWRlW5zykq/ii0jMoX5cYt9yd0xR7splqpPe7RwZv/wYKVEtwxB0q1EcbtK3ORRwx1 NVtw== X-Gm-Message-State: APjAAAWFBjMLNsSD+UM3eV0Ct2JSS1iK8SaPyVGEeCMkJKXQmTedGs6s j3hMhRKTC0G6pvd62c41V938CA== X-Google-Smtp-Source: APXvYqzuRG4Hg6s83vAFpmHfOYCDXPS45JNvrstZincUSwNl/Wd/1CFnObVppEOsYuJ/kLkK6LO0Kw== X-Received: by 2002:a17:902:988a:: with SMTP id s10mr76931523plp.304.1560264859282; Tue, 11 Jun 2019 07:54:19 -0700 (PDT) Received: from localhost.localdomain ([115.97.180.18]) by smtp.gmail.com with ESMTPSA id e9sm16206208pfn.154.2019.06.11.07.54.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Jun 2019 07:54:18 -0700 (PDT) From: Jagan Teki To: Simon Glass , Philipp Tomsich , Kever Yang , YouMin Chen , u-boot@lists.denx.de Date: Tue, 11 Jun 2019 20:20:40 +0530 Message-Id: <20190611145135.21399-38-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190611145135.21399-1-jagan@amarulasolutions.com> References: <20190611145135.21399-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Cc: linux-rockchip@lists.infradead.org, linux-amarula@amarulasolutions.com, gajjar04akash@gmail.com Subject: [U-Boot] [PATCH 37/92] ram: rockchip: rk3399: Add cap_info structure X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Group common ddr attributes like - rank - col - bk - bw - dbw - row_3_4 - cs0_row - cs1_row - ddrconfig into a common cap_info structure for more code readability and extend if possible based on the new features. No functionality change. Signed-off-by: Jagan Teki --- .../include/asm/arch-rockchip/sdram_rk3399.h | 6 +- drivers/ram/rockchip/sdram_rk3399.c | 71 ++++++++++--------- 2 files changed, 41 insertions(+), 36 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h index a191d242f8..67044f53e5 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h @@ -96,7 +96,7 @@ struct rk3399_ddr_cic_regs { /* DENALI_CTL_274 */ #define MEM_RST_VALID 1 -struct rk3399_sdram_channel { +struct sdram_cap_info { unsigned int rank; /* dram column number, 0 means this channel is invalid */ unsigned int col; @@ -114,6 +114,10 @@ struct rk3399_sdram_channel { unsigned int cs0_row; unsigned int cs1_row; unsigned int ddrconfig; +}; + +struct rk3399_sdram_channel { + struct sdram_cap_info cap_info; struct rk3399_msch_timings noc_timings; }; diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 220197a42e..1acf9efe9c 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -156,35 +156,36 @@ static void set_memory_map(const struct chan_info *chan, u32 channel, u32 row; /* Get row number from ddrconfig setting */ - if (sdram_ch->ddrconfig < 2 || sdram_ch->ddrconfig == 4) + if (sdram_ch->cap_info.ddrconfig < 2 || + sdram_ch->cap_info.ddrconfig == 4) row = 16; - else if (sdram_ch->ddrconfig == 3) + else if (sdram_ch->cap_info.ddrconfig == 3) row = 14; else row = 15; - cs_map = (sdram_ch->rank > 1) ? 3 : 1; - reduc = (sdram_ch->bw == 2) ? 0 : 1; + cs_map = (sdram_ch->cap_info.rank > 1) ? 3 : 1; + reduc = (sdram_ch->cap_info.bw == 2) ? 0 : 1; /* Set the dram configuration to ctrl */ - clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->col)); + clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->cap_info.col)); clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24), - ((3 - sdram_ch->bk) << 16) | + ((3 - sdram_ch->cap_info.bk) << 16) | ((16 - row) << 24)); clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16), cs_map | (reduc << 16)); /* PI_199 PI_COL_DIFF:RW:0:4 */ - clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->col)); + clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->cap_info.col)); /* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */ clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24), - ((3 - sdram_ch->bk) << 16) | + ((3 - sdram_ch->cap_info.bk) << 16) | ((16 - row) << 24)); /* PI_41 PI_CS_MAP:RW:24:4 */ clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24); - if (sdram_ch->rank == 1 && sdram_params->base.dramtype == DDR3) + if (sdram_ch->cap_info.rank == 1 && sdram_params->base.dramtype == DDR3) writel(0x2EC7FFFF, &denali_pi[34]); } @@ -686,7 +687,7 @@ static int data_training_ca(const struct chan_info *chan, u32 channel, u32 *denali_phy = chan->publ->denali_phy; u32 i, tmp; u32 obs_0, obs_1, obs_2, obs_err = 0; - u32 rank = sdram_params->ch[channel].rank; + u32 rank = sdram_params->ch[channel].cap_info.rank; u32 rank_mask; /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ @@ -749,7 +750,7 @@ static int data_training_wl(const struct chan_info *chan, u32 channel, u32 *denali_phy = chan->publ->denali_phy; u32 i, tmp; u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0; - u32 rank = sdram_params->ch[channel].rank; + u32 rank = sdram_params->ch[channel].cap_info.rank; /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ writel(0x00003f7c, (&denali_pi[175])); @@ -811,7 +812,7 @@ static int data_training_rg(const struct chan_info *chan, u32 channel, u32 *denali_phy = chan->publ->denali_phy; u32 i, tmp; u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0; - u32 rank = sdram_params->ch[channel].rank; + u32 rank = sdram_params->ch[channel].cap_info.rank; /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ writel(0x00003f7c, (&denali_pi[175])); @@ -873,7 +874,7 @@ static int data_training_rl(const struct chan_info *chan, u32 channel, { u32 *denali_pi = chan->pi->denali_pi; u32 i, tmp; - u32 rank = sdram_params->ch[channel].rank; + u32 rank = sdram_params->ch[channel].cap_info.rank; /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ writel(0x00003f7c, (&denali_pi[175])); @@ -921,7 +922,7 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel, { u32 *denali_pi = chan->pi->denali_pi; u32 i, tmp; - u32 rank = sdram_params->ch[channel].rank; + u32 rank = sdram_params->ch[channel].cap_info.rank; u32 rank_mask; /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ @@ -1055,14 +1056,14 @@ static void set_ddrconfig(const struct chan_info *chan, unsigned int cs0_cap = 0; unsigned int cs1_cap = 0; - cs0_cap = (1 << (sdram_params->ch[channel].cs0_row - + sdram_params->ch[channel].col - + sdram_params->ch[channel].bk - + sdram_params->ch[channel].bw - 20)); - if (sdram_params->ch[channel].rank > 1) - cs1_cap = cs0_cap >> (sdram_params->ch[channel].cs0_row - - sdram_params->ch[channel].cs1_row); - if (sdram_params->ch[channel].row_3_4) { + cs0_cap = (1 << (sdram_params->ch[channel].cap_info.cs0_row + + sdram_params->ch[channel].cap_info.col + + sdram_params->ch[channel].cap_info.bk + + sdram_params->ch[channel].cap_info.bw - 20)); + if (sdram_params->ch[channel].cap_info.rank > 1) + cs1_cap = cs0_cap >> (sdram_params->ch[channel].cap_info.cs0_row + - sdram_params->ch[channel].cap_info.cs1_row); + if (sdram_params->ch[channel].cap_info.row_3_4) { cs0_cap = cs0_cap * 3 / 4; cs1_cap = cs1_cap * 3 / 4; } @@ -1089,22 +1090,22 @@ static void dram_all_config(struct dram_info *dram, struct rk3399_msch_regs *ddr_msch_regs; const struct rk3399_msch_timings *noc_timing; - if (sdram_params->ch[channel].col == 0) + if (sdram_params->ch[channel].cap_info.col == 0) continue; idx++; - sys_reg2 |= SYS_REG_ENC_ROW_3_4(info->row_3_4, channel); + sys_reg2 |= SYS_REG_ENC_ROW_3_4(info->cap_info.row_3_4, channel); sys_reg2 |= SYS_REG_ENC_CHINFO(channel); - sys_reg2 |= SYS_REG_ENC_RANK(info->rank, channel); - sys_reg2 |= SYS_REG_ENC_COL(info->col, channel); - sys_reg2 |= SYS_REG_ENC_BK(info->bk, channel); - sys_reg2 |= SYS_REG_ENC_BW(info->bw, channel); - sys_reg2 |= SYS_REG_ENC_DBW(info->dbw, channel); - SYS_REG_ENC_CS0_ROW(info->cs0_row, sys_reg2, sys_reg3, channel); - if (info->cs1_row) - SYS_REG_ENC_CS1_ROW(info->cs1_row, sys_reg2, + sys_reg2 |= SYS_REG_ENC_RANK(info->cap_info.rank, channel); + sys_reg2 |= SYS_REG_ENC_COL(info->cap_info.col, channel); + sys_reg2 |= SYS_REG_ENC_BK(info->cap_info.bk, channel); + sys_reg2 |= SYS_REG_ENC_BW(info->cap_info.bw, channel); + sys_reg2 |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel); + SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, sys_reg2, sys_reg3, channel); + if (info->cap_info.cs1_row) + SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, sys_reg2, sys_reg3, channel); - sys_reg3 |= SYS_REG_ENC_CS1_COL(info->col, channel); + sys_reg3 |= SYS_REG_ENC_CS1_COL(info->cap_info.col, channel); sys_reg3 |= SYS_REG_ENC_VERSION(DDR_SYS_REG_VERSION); ddr_msch_regs = dram->chan[channel].msch; @@ -1121,7 +1122,7 @@ static void dram_all_config(struct dram_info *dram, &ddr_msch_regs->ddrmode); /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */ - if (sdram_params->ch[channel].rank == 1) + if (sdram_params->ch[channel].cap_info.rank == 1) setbits_le32(&dram->chan[channel].pctl->denali_ctl[276], 1 << 17); } @@ -1232,7 +1233,7 @@ static int sdram_init(struct dram_info *dram, } set_ddrconfig(chan, sdram_params, channel, - sdram_params->ch[channel].ddrconfig); + sdram_params->ch[channel].cap_info.ddrconfig); } dram_all_config(dram, sdram_params); switch_to_phy_index1(dram, sdram_params);