From patchwork Tue Jun 11 14:50:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1113926 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="fWT8VJYS"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45NYMn3QMzz9s6w for ; Wed, 12 Jun 2019 01:10:13 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id D31B0C220BA; Tue, 11 Jun 2019 14:56:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 7F0E5C21C8B; Tue, 11 Jun 2019 14:55:48 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id CF108C21E2B; Tue, 11 Jun 2019 14:54:12 +0000 (UTC) Received: from mail-pf1-f195.google.com (mail-pf1-f195.google.com [209.85.210.195]) by lists.denx.de (Postfix) with ESMTPS id BD129C21DED for ; Tue, 11 Jun 2019 14:54:08 +0000 (UTC) Received: by mail-pf1-f195.google.com with SMTP id 81so7575904pfy.13 for ; Tue, 11 Jun 2019 07:54:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ckb/dVtuw942Plu9XgJ6pHzs/1bm+A1p+7DNE1ADw90=; b=fWT8VJYSmMzJAYNC80m2AzxvuKviRv1U4jSTik65lKbCMdRPWGSKqLdY0CWuW3SmYG Zu1zDSK29DPG2h7SHB+Rs8gOZh38hd8sYdsUEwUgPzPfAqMpE+V7VyPI3CmkDu57e8Ma xkD+AXCM2x89snotE2vfD18fPKGj4J1JGMiHQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ckb/dVtuw942Plu9XgJ6pHzs/1bm+A1p+7DNE1ADw90=; b=RsGNEADsfga5Kw3KLGGQsUho3M5CW50l0qK6LpVffGvaTGTe7MAbg/bzLP70+nOXCq cNeSnEsNUYax3uRqsm3W+fcrNLeGG6701gXTGZceeGIx2kGSRIWuKOIYLfXWhHFKWhGc S9cuGFDQX/GCzqsPPu9Lt5B7FrnEcbm1DaYxbOamTmZhUknsVbZzIdeNKm03Ja8HR15w 2WfzpAa6vrSd9/RcF5JyeVW6Zz1U4C8LEzuSjYc3x2yrrAJUH3Swx2mbZrwo9ynopi6P 0XTG4gNHxBh2Fn+GtjdEOVeowolQytN7AoJZLfR4x8NL4U1AewLERe64D7ilFEwSLlqD uHYw== X-Gm-Message-State: APjAAAUPBndedSf6B3/f2PZIqTlsgFDPSA5M+mj3SpiSimGdCOsT05Jj AIhV0zJdgHqPEw5tpVefW27/+w== X-Google-Smtp-Source: APXvYqx6VkHOMAsdNKttuOPOGpRsMDbET+LXthED6rYa89xIpORcS9/+u0D+UP890ROSguwOZKxq6A== X-Received: by 2002:a63:2b8a:: with SMTP id r132mr20451397pgr.196.1560264847320; Tue, 11 Jun 2019 07:54:07 -0700 (PDT) Received: from localhost.localdomain ([115.97.180.18]) by smtp.gmail.com with ESMTPSA id e9sm16206208pfn.154.2019.06.11.07.54.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Jun 2019 07:54:06 -0700 (PDT) From: Jagan Teki To: Simon Glass , Philipp Tomsich , Kever Yang , YouMin Chen , u-boot@lists.denx.de Date: Tue, 11 Jun 2019 20:20:37 +0530 Message-Id: <20190611145135.21399-35-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190611145135.21399-1-jagan@amarulasolutions.com> References: <20190611145135.21399-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Cc: linux-rockchip@lists.infradead.org, linux-amarula@amarulasolutions.com, gajjar04akash@gmail.com Subject: [U-Boot] [PATCH 34/92] ram: rk3399: Add phy pctrl reset support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add support for phy pctrl reset support for both channel 0, 1. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen --- drivers/ram/rockchip/sdram_rk3399.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index e3945feca3..bbf56f29ae 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -35,6 +35,10 @@ #define PHY_DRV_ODT_40 0xe #define PHY_DRV_ODT_34_3 0xf +#define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \ + ((n) << (8 + (ch) * 4))) +#define CRU_SFTRST_DDR_PHY(ch, n) ((0x1 << (9 + 16 + (ch) * 4)) | \ + ((n) << (9 + (ch) * 4))) struct chan_info { struct rk3399_ddr_pctl_regs *pctl; struct rk3399_ddr_pi_regs *pi; @@ -79,6 +83,29 @@ static void copy_to_reg(u32 *dest, const u32 *src, u32 n) } } +static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl, + u32 phy) +{ + channel &= 0x1; + ctl &= 0x1; + phy &= 0x1; + writel(CRU_SFTRST_DDR_CTRL(channel, ctl) | + CRU_SFTRST_DDR_PHY(channel, phy), + &cru->softrst_con[4]); +} + +static void phy_pctrl_reset(struct rk3399_cru *cru, u32 channel) +{ + rkclk_ddr_reset(cru, channel, 1, 1); + udelay(10); + + rkclk_ddr_reset(cru, channel, 1, 0); + udelay(10); + + rkclk_ddr_reset(cru, channel, 0, 0); + udelay(10); +} + static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs, u32 freq) { @@ -1126,6 +1153,7 @@ static int sdram_init(struct dram_info *dram, { unsigned char dramtype = sdram_params->base.dramtype; unsigned int ddr_freq = sdram_params->base.ddr_freq; + struct rk3399_cru *cru = dram->cru; int channel; int ret; @@ -1142,6 +1170,7 @@ static int sdram_init(struct dram_info *dram, const struct chan_info *chan = &dram->chan[channel]; struct rk3399_ddr_publ_regs *publ = chan->publ; + phy_pctrl_reset(cru, channel); phy_dll_bypass_set(publ, ddr_freq); if (channel >= sdram_params->base.num_channels)