From patchwork Tue Jun 11 14:50:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1113936 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="jl1WRHH2"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45NYS635g3z9s5c for ; Wed, 12 Jun 2019 01:13:58 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id BF13EC2210C; Tue, 11 Jun 2019 15:04:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B087AC220C4; Tue, 11 Jun 2019 15:03:48 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id BCEA0C21E02; Tue, 11 Jun 2019 14:54:00 +0000 (UTC) Received: from mail-pf1-f193.google.com (mail-pf1-f193.google.com [209.85.210.193]) by lists.denx.de (Postfix) with ESMTPS id 65E4DC21E45 for ; Tue, 11 Jun 2019 14:53:56 +0000 (UTC) Received: by mail-pf1-f193.google.com with SMTP id s11so7573049pfm.12 for ; Tue, 11 Jun 2019 07:53:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Vq2oI+3vMUMkg0n1XXuFvNc3vyzrVc/D6owKjBX1t4g=; b=jl1WRHH2HKGT3KTDigMBc6mdpZFY9R4qaxLGPRjFqiwI4+dru0Vehtkex9T9p5JbCd LRfAzW/zxpUGOIyTFHEO/JtHKDRzecp3RvPY8haaEx0harcbb0mgX+QEsrsTSI/NotTn 3jWEpKNCRJkK2Bj7dAi/n2lV54GnF7CR5KQU0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Vq2oI+3vMUMkg0n1XXuFvNc3vyzrVc/D6owKjBX1t4g=; b=joz5nF+4IsCMFT+1phBGJwiJtgI2C8F1BmdkJ9w7unLxsk/Wrvec+TJbtUTFzu+p6s KqjUznmtimM5AeOJ8c58mdKQpjHya2HauNqGFmE0GCrgkjJtrI3hON+Fx0BnIrHJWkgf 44+3rUvN0ZDL1pDiJN4ssbL9U0shlg0engXUKOBJLrjM2DsgZrXhOStsKNRfMDwChsFQ s4+9HvaCHp3yzNPQOVs1K4xSl0u0RqbAUdRhX2WljRQK9lAKnAq/YvT5BxkDDnx7HCWI Yx+EG6MewFKDhUujOT9yaJe+c6USDl6M5zA04yV5GoY0EbnxUi00OTWA5rsFSTg/uDh6 UATA== X-Gm-Message-State: APjAAAVTe0dFrl7Okpevsc1lTdKGrdWU5j/yTxG3GQy4j81EKwdwPGFH 1YhRt1OV73B3t4GiJfFaD4ZVqQ== X-Google-Smtp-Source: APXvYqwq1L9EuxxW0dNWzHadMSldjCMaQ8fw0phMMVozqqhNI58K+zamMktr54IMdBpCMDNN//A46g== X-Received: by 2002:a62:e815:: with SMTP id c21mr38798237pfi.244.1560264835030; Tue, 11 Jun 2019 07:53:55 -0700 (PDT) Received: from localhost.localdomain ([115.97.180.18]) by smtp.gmail.com with ESMTPSA id e9sm16206208pfn.154.2019.06.11.07.53.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Jun 2019 07:53:54 -0700 (PDT) From: Jagan Teki To: Simon Glass , Philipp Tomsich , Kever Yang , YouMin Chen , u-boot@lists.denx.de Date: Tue, 11 Jun 2019 20:20:34 +0530 Message-Id: <20190611145135.21399-32-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190611145135.21399-1-jagan@amarulasolutions.com> References: <20190611145135.21399-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Cc: linux-rockchip@lists.infradead.org, linux-amarula@amarulasolutions.com, gajjar04akash@gmail.com Subject: [U-Boot] [PATCH 31/92] ram: rk3399: s/ca_tsel_wr_select_n/tsel_wr_select_ca_n X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Rename ca_tsel_wr_select_n to tsel_wr_select_ca_n based on the bsp code and associated datasheet. No functionality change. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen --- drivers/ram/rockchip/sdram_rk3399.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 780b18fa17..bfae4e78a9 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -161,7 +161,7 @@ static void set_ds_odt(const struct chan_info *chan, u32 tsel_idle_en, tsel_wr_en, tsel_rd_en; u32 tsel_idle_select_p, tsel_wr_select_dq_p, tsel_rd_select_p; - u32 ca_tsel_wr_select_p, ca_tsel_wr_select_n; + u32 ca_tsel_wr_select_p, tsel_wr_select_ca_n; u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n; u32 reg_value; @@ -173,7 +173,7 @@ static void set_ds_odt(const struct chan_info *chan, tsel_rd_select_n = PHY_DRV_ODT_240; tsel_wr_select_dq_n = PHY_DRV_ODT_40; - ca_tsel_wr_select_n = PHY_DRV_ODT_40; + tsel_wr_select_ca_n = PHY_DRV_ODT_40; tsel_idle_select_n = PHY_DRV_ODT_240; } else if (sdram_params->base.dramtype == LPDDR3) { tsel_rd_select_p = PHY_DRV_ODT_240; @@ -183,7 +183,7 @@ static void set_ds_odt(const struct chan_info *chan, tsel_rd_select_n = PHY_DRV_ODT_HI_Z; tsel_wr_select_dq_n = PHY_DRV_ODT_34_3; - ca_tsel_wr_select_n = PHY_DRV_ODT_48; + tsel_wr_select_ca_n = PHY_DRV_ODT_48; tsel_idle_select_n = PHY_DRV_ODT_HI_Z; } else { tsel_rd_select_p = PHY_DRV_ODT_240; @@ -193,7 +193,7 @@ static void set_ds_odt(const struct chan_info *chan, tsel_rd_select_n = PHY_DRV_ODT_240; tsel_wr_select_dq_n = PHY_DRV_ODT_34_3; - ca_tsel_wr_select_n = PHY_DRV_ODT_34_3; + tsel_wr_select_ca_n = PHY_DRV_ODT_34_3; tsel_idle_select_n = PHY_DRV_ODT_240; } @@ -229,7 +229,7 @@ static void set_ds_odt(const struct chan_info *chan, clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value); /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */ - reg_value = ca_tsel_wr_select_n | (ca_tsel_wr_select_p << 0x4); + reg_value = tsel_wr_select_ca_n | (ca_tsel_wr_select_p << 0x4); clrsetbits_le32(&denali_phy[544], 0xff, reg_value); clrsetbits_le32(&denali_phy[672], 0xff, reg_value); clrsetbits_le32(&denali_phy[800], 0xff, reg_value);