From patchwork Fri May 31 16:00:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 1108424 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=ziswiler.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45Fq1D6vPgz9s3l for ; Sat, 1 Jun 2019 02:00:48 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id A1AB6C21DD4; Fri, 31 May 2019 16:00:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=SPF_HELO_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D4523C21C51; Fri, 31 May 2019 16:00:44 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4B080C21C51; Fri, 31 May 2019 16:00:43 +0000 (UTC) Received: from mout.perfora.net (mout.perfora.net [74.208.4.196]) by lists.denx.de (Postfix) with ESMTPS id A161CC21BE5 for ; Fri, 31 May 2019 16:00:42 +0000 (UTC) Received: from marcel-nb-toradex-int.toradex.int ([194.105.145.87]) by mrelay.perfora.net (mreueus004 [74.208.5.2]) with ESMTPSA (Nemesis) id 1MHnyM-1hLEhD1fhm-00ExyN; Fri, 31 May 2019 18:00:34 +0200 From: Marcel Ziswiler To: u-boot@lists.denx.de Date: Fri, 31 May 2019 19:00:15 +0300 Message-Id: <20190531160020.9755-2-marcel@ziswiler.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190531160020.9755-1-marcel@ziswiler.com> References: <20190531160020.9755-1-marcel@ziswiler.com> MIME-Version: 1.0 X-Provags-ID: V03:K1:PWk8bfsDPh+dcKb835UjyGlt5WAuBS9kOKbdbc0svHE79F/2gDe Wvk0ajPeE+Cm54R22T4W0VmwaJ8GPs0sA4UfTIEbgcxx1BHMm4iTy57FDbuvWpcbUmWnTl/ Wvkj18xsKr6LI1qewVTD1z5SryWUxYnZsN5vbtxtJSGiwAbkZzvxC11absA78gZQgqCxN2t TrzBTqoDCdhlPNnnR6PuQ== X-UI-Out-Filterresults: notjunk:1; V03:K0:WM4B/DEmZWA=:gv/kLcY4BVLctrBvFV3W5E Arw4Tb/O+AlHWwKMOcCqPe/SI4WQy2ayceTG0ykuEtdPYiqtACR2s8JlKoes1EJ8kcLuudYME 3JxDolH84q0lLIFurAc2p2Z1yuMqBTmEsk85jGfovj74qJNK8LaAnQ85MNDxYFMnQFnAhvQpm 1lci/037ee9Qg8iqHEPUYEU3BuRtAboCcnASHNJKi0PLAkSxpfOG12HSgd1I+It2bB1a4Dx6B e6n3i63dAwcIkGubhzYOszPxOiVRSye75tTZ/Oui6C6ShOSAjp0Sks9AnGQsLa3R624MqO41G 4AaQffmkWgzOpo5p9HtigZQmH51Y8+tcO1hfKqMju9wubeYWHlMCWSnUKYEAi64Icx3Fj2xG9 S9aAiP3tVjONOShPiyLhiK9+0OkoEceumBgvVhpobS+PIpQ4ShcPamU+k5ioiyevsVUS4Fa6D jEVR6BuksMuNsXMsJEyDLD5gCeH+4sW3IAz/oreMOLuQ+JheAAL3Xy+XN2LYyxf4wHvvU81wa oJcIfl7y/xofwWQXOuBGuO3ZVCnCDb3ZYcQ3meoKXswlvRR23uWwgw3qednZm9TG/WXwwWfQ4 zRSHut7jiZqiN5OMIvXQKUJKYt220HnkEbhoYoNHBttozJW+egCOHv8rbVMxATBcpuFFCBI8g 1vaxFUFzz8HbP1mOXBm+mm4sK+15ViP5O7tvuhZ7Vh9tqKWlvoG7KcI6jlZwqFljlCqq6WmDh enei1YbDqwDrQjQ5xdTIn5denl+sQQXVxB13kA== Cc: Tom Rini , Marcel Ziswiler , Max Krummenacher , Fabio Estevam Subject: [U-Boot] [PATCH v3 1/6] arm: dts: imx8qm: add lpuart1, lpuart2, lpuart3, lpuart4 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Marcel Ziswiler Add support for lpuart1, lpuart2, lpuart3 and lpuart4. Signed-off-by: Marcel Ziswiler Reviewed-by: Max Krummenacher --- Changes in v3: None Changes in v2: None arch/arm/dts/fsl-imx8qm.dtsi | 80 ++++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm/dts/fsl-imx8qm.dtsi b/arch/arm/dts/fsl-imx8qm.dtsi index b39c40bd98..db01959990 100644 --- a/arch/arm/dts/fsl-imx8qm.dtsi +++ b/arch/arm/dts/fsl-imx8qm.dtsi @@ -22,6 +22,10 @@ ethernet0 = &fec1; ethernet1 = &fec2; serial0 = &lpuart0; + serial1 = &lpuart1; + serial2 = &lpuart2; + serial3 = &lpuart3; + serial4 = &lpuart4; mmc0 = &usdhc1; mmc1 = &usdhc2; mmc2 = &usdhc3; @@ -193,6 +197,30 @@ power-domains = <&pd_dma>; wakeup-irq = <345>; }; + pd_dma_lpuart1: PD_DMA_UART1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + wakeup-irq = <346>; + }; + pd_dma_lpuart2: PD_DMA_UART2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + wakeup-irq = <347>; + }; + pd_dma_lpuart3: PD_DMA_UART3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + wakeup-irq = <348>; + }; + pd_dma_lpuart4: PD_DMA_UART4 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + wakeup-irq = <349>; + }; }; }; @@ -297,6 +325,58 @@ status = "disabled"; }; + lpuart1: serial@5a070000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a070000 0x0 0x1000>; + interrupts = ; + clocks = <&clk IMX8QM_UART1_CLK>, + <&clk IMX8QM_UART1_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_UART1_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart1>; + status = "disabled"; + }; + + lpuart2: serial@5a080000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a080000 0x0 0x1000>; + interrupts = ; + clocks = <&clk IMX8QM_UART2_CLK>, + <&clk IMX8QM_UART2_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_UART2_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart2>; + status = "disabled"; + }; + + lpuart3: serial@5a090000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a090000 0x0 0x1000>; + interrupts = ; + clocks = <&clk IMX8QM_UART3_CLK>, + <&clk IMX8QM_UART3_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_UART3_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart3>; + status = "disabled"; + }; + + lpuart4: serial@5a0a0000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a0a0000 0x0 0x1000>; + interrupts = ; + clocks = <&clk IMX8QM_UART4_CLK>, + <&clk IMX8QM_UART4_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_UART4_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart4>; + status = "disabled"; + }; + usdhc1: usdhc@5b010000 { compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; interrupt-parent = <&gic>;