From patchwork Wed May 22 18:37:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 1103506 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="Y87KYUQ/"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 458M392yjMz9sCJ for ; Thu, 23 May 2019 04:43:33 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 107CAC21E47; Wed, 22 May 2019 18:38:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B07E6C21E4E; Wed, 22 May 2019 18:37:16 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id CF866C21C2C; Wed, 22 May 2019 18:37:12 +0000 (UTC) Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lists.denx.de (Postfix) with ESMTPS id CE5DFC21D9A for ; Wed, 22 May 2019 18:37:11 +0000 (UTC) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x4MIbAHA004029; Wed, 22 May 2019 13:37:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1558550230; bh=YmRqhDAzHxi4b7+LhJRpqjgNd/Rx3V7RWd9PNy5MQMk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Y87KYUQ/OQHbgJ7QhQ/AU1efbkqd50ykryw+1lHSWNs/iiarhrr6/EalBvWinwaHg OJrVzBFYmPRDWxpUtt3yWaGJWm3lmmJnVSjXH5zKOFH1geVl0vfs5oe+0vZ15CqWTX mWMKNB3IjhMktpMWMdp8CkJXdB4mOICZjM2BzumA= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x4MIbAxx103574 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 22 May 2019 13:37:10 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 22 May 2019 13:37:09 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 22 May 2019 13:37:09 -0500 Received: from a0131933.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x4MIb8Mb096383; Wed, 22 May 2019 13:37:09 -0500 From: Lokesh Vutla To: Tom Rini , Date: Wed, 22 May 2019 13:37:01 -0500 Message-ID: <20190522183707.19326-9-lokeshvutla@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190522183707.19326-1-lokeshvutla@ti.com> References: <20190522183707.19326-1-lokeshvutla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Tero Kristo Subject: [U-Boot] [PATCH 08/14] mmc: am654_sdhci: Separate J721E compatible into 8bit and 4bit versions X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Faiz Abbas The j721e 4 bit instances don't have a hard DLL and therefore don't need any DLL related configurations. Split the compatibles into an 8 bit and a 4 bit one. Add a private flags field which can be used to check if the DLL is present and don't register the set_ios_post callback for the 4 bit compatible instances. Also update the compatibles in k3-j721e-main.dtsi to avoid breaking boot with the new compatibles. Signed-off-by: Faiz Abbas Signed-off-by: Lokesh Vutla --- drivers/mmc/am654_sdhci.c | 114 ++++++++++++++++++++++++-------------- 1 file changed, 71 insertions(+), 43 deletions(-) diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c index cc62120718..ceb5584751 100644 --- a/drivers/mmc/am654_sdhci.c +++ b/drivers/mmc/am654_sdhci.c @@ -73,6 +73,8 @@ struct am654_sdhci_plat { u32 otap_del_sel; u32 trm_icp; u32 drv_strength; + u32 flags; +#define DLL_PRESENT (1 << 0) bool dll_on; }; @@ -163,6 +165,10 @@ const struct sdhci_ops am654_sdhci_ops = { .set_control_reg = &am654_sdhci_set_control_reg, }; +const struct sdhci_ops j721e_4bit_sdhci_ops = { + .set_control_reg = &am654_sdhci_set_control_reg, +}; + int am654_sdhci_init(struct am654_sdhci_plat *plat) { u32 ctl_cfg_2 = 0; @@ -173,24 +179,28 @@ int am654_sdhci_init(struct am654_sdhci_plat *plat) mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; regmap_update_bits(plat->base, PHY_CTRL4, mask, 0x0); - regmap_read(plat->base, PHY_STAT1, &val); - if (~val & CALDONE_MASK) { - /* Calibrate IO lines */ - regmap_update_bits(plat->base, PHY_CTRL1, PDB_MASK, PDB_MASK); - ret = regmap_read_poll_timeout(plat->base, PHY_STAT1, val, - val & CALDONE_MASK, 1, 20); - if (ret) - return ret; - } + if (plat->flags & DLL_PRESENT) { + regmap_read(plat->base, PHY_STAT1, &val); + if (~val & CALDONE_MASK) { + /* Calibrate IO lines */ + regmap_update_bits(plat->base, PHY_CTRL1, PDB_MASK, + PDB_MASK); + ret = regmap_read_poll_timeout(plat->base, PHY_STAT1, + val, val & CALDONE_MASK, + 1, 20); + if (ret) + return ret; + } - /* Configure DLL TRIM */ - mask = DLL_TRIM_ICP_MASK; - val = plat->trm_icp << DLL_TRIM_ICP_SHIFT; + /* Configure DLL TRIM */ + mask = DLL_TRIM_ICP_MASK; + val = plat->trm_icp << DLL_TRIM_ICP_SHIFT; - /* Configure DLL driver strength */ - mask |= DR_TY_MASK; - val |= plat->drv_strength << DR_TY_SHIFT; - regmap_update_bits(plat->base, PHY_CTRL1, mask, val); + /* Configure DLL driver strength */ + mask |= DR_TY_MASK; + val |= plat->drv_strength << DR_TY_SHIFT; + regmap_update_bits(plat->base, PHY_CTRL1, mask, val); + } /* Enable pins by setting IO mux to 0 */ regmap_update_bits(plat->base, PHY_CTRL1, IOMUX_ENABLE_MASK, 0); @@ -246,7 +256,7 @@ static int am654_sdhci_probe(struct udevice *dev) AM654_SDHCI_MIN_FREQ); if (ret) return ret; - host->ops = &am654_sdhci_ops; + host->ops = (struct sdhci_ops *)dev_get_driver_data(dev); host->mmc->priv = host; upriv->mmc = host->mmc; @@ -269,37 +279,44 @@ static int am654_sdhci_ofdata_to_platdata(struct udevice *dev) host->ioaddr = (void *)dev_read_addr(dev); plat->non_removable = dev_read_bool(dev, "non-removable"); - ret = dev_read_u32(dev, "ti,trm-icp", &plat->trm_icp); - if (ret) - return ret; + if (device_is_compatible(dev, "ti,am654-sdhci-5.1") || + device_is_compatible(dev, "ti,j721e-sdhci-8bit")) + plat->flags |= DLL_PRESENT; ret = dev_read_u32(dev, "ti,otap-del-sel", &plat->otap_del_sel); if (ret) return ret; - ret = dev_read_u32(dev, "ti,driver-strength-ohm", &drv_strength); - if (ret) - return ret; + if (plat->flags & DLL_PRESENT) { + ret = dev_read_u32(dev, "ti,trm-icp", &plat->trm_icp); + if (ret) + return ret; + + ret = dev_read_u32(dev, "ti,driver-strength-ohm", + &drv_strength); + if (ret) + return ret; - switch (drv_strength) { - case 50: - plat->drv_strength = DRIVER_STRENGTH_50_OHM; - break; - case 33: - plat->drv_strength = DRIVER_STRENGTH_33_OHM; - break; - case 66: - plat->drv_strength = DRIVER_STRENGTH_66_OHM; - break; - case 100: - plat->drv_strength = DRIVER_STRENGTH_100_OHM; - break; - case 40: - plat->drv_strength = DRIVER_STRENGTH_40_OHM; - break; - default: - dev_err(dev, "Invalid driver strength\n"); - return -EINVAL; + switch (drv_strength) { + case 50: + plat->drv_strength = DRIVER_STRENGTH_50_OHM; + break; + case 33: + plat->drv_strength = DRIVER_STRENGTH_33_OHM; + break; + case 66: + plat->drv_strength = DRIVER_STRENGTH_66_OHM; + break; + case 100: + plat->drv_strength = DRIVER_STRENGTH_100_OHM; + break; + case 40: + plat->drv_strength = DRIVER_STRENGTH_40_OHM; + break; + default: + dev_err(dev, "Invalid driver strength\n"); + return -EINVAL; + } } ret = mmc_of_parse(dev, cfg); @@ -317,7 +334,18 @@ static int am654_sdhci_bind(struct udevice *dev) } static const struct udevice_id am654_sdhci_ids[] = { - { .compatible = "ti,am654-sdhci-5.1" }, + { + .compatible = "ti,am654-sdhci-5.1", + .data = (ulong)&am654_sdhci_ops, + }, + { + .compatible = "ti,j721e-sdhci-8bit", + .data = (ulong)&am654_sdhci_ops, + }, + { + .compatible = "ti,j721e-sdhci-4bit", + .data = (ulong)&j721e_4bit_sdhci_ops, + }, { } };