From patchwork Wed May 22 18:36:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 1103500 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="r8rn294D"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 458M1M44K6z9sML for ; Thu, 23 May 2019 04:41:59 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 36BEDC21E31; Wed, 22 May 2019 18:40:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 8D73EC21DD7; Wed, 22 May 2019 18:37:20 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 848DAC21C50; Wed, 22 May 2019 18:37:13 +0000 (UTC) Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lists.denx.de (Postfix) with ESMTPS id 945F6C21C50 for ; Wed, 22 May 2019 18:37:12 +0000 (UTC) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x4MIb9GZ070326; Wed, 22 May 2019 13:37:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1558550229; bh=VNKDO3089DzU+mVcLFcqKaofI86yzrJ9n/REygeJGCw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=r8rn294D6UGLXLY4QuT1PHlQza8upkjNVF7moIQzXGQ5SN1lEXsokk17IXCCIy60O YIW4do6q4LydSVYnLO3WQh1mBGdA5+NIBRS/Xaa6YNWOL8OPobMf25j7jPKHzmpaLi 9yhPCYdjH9LdQSqR/rTCmnRaCW6PXeI1RQiip31Q= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x4MIb992103568 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 22 May 2019 13:37:09 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 22 May 2019 13:37:09 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 22 May 2019 13:37:09 -0500 Received: from a0131933.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x4MIb8MZ096383; Wed, 22 May 2019 13:37:09 -0500 From: Lokesh Vutla To: Tom Rini , Date: Wed, 22 May 2019 13:36:59 -0500 Message-ID: <20190522183707.19326-7-lokeshvutla@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190522183707.19326-1-lokeshvutla@ti.com> References: <20190522183707.19326-1-lokeshvutla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Tero Kristo Subject: [U-Boot] [PATCH 06/14] armv7R: K3: j721e: Shut down R5 core after ATF startup on A72 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Populate the release_resources_for_core_shutdown() api with shutting down r5 cores so that it will by called just after jumping to ATF. Signed-off-by: Lokesh Vutla --- arch/arm/mach-k3/j721e_init.c | 57 +++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c index 211ca448aa..b20c941846 100644 --- a/arch/arm/mach-k3/j721e_init.c +++ b/arch/arm/mach-k3/j721e_init.c @@ -12,6 +12,8 @@ #include #include #include "common.h" +#include +#include #ifdef CONFIG_SPL_BUILD static void mmr_unlock(u32 base, u32 partition) @@ -139,3 +141,58 @@ u32 spl_boot_device(void) return __get_primary_bootmedia(main_devstat, wkup_devstat); } #endif + +#ifdef CONFIG_SYS_K3_SPL_ATF + +#define J721E_DEV_MCU_RTI0 262 +#define J721E_DEV_MCU_RTI1 263 +#define J721E_DEV_MCU_ARMSS0_CPU0 250 +#define J721E_DEV_MCU_ARMSS0_CPU1 251 + +void release_resources_for_core_shutdown(void) +{ + struct ti_sci_handle *ti_sci; + struct ti_sci_dev_ops *dev_ops; + struct ti_sci_proc_ops *proc_ops; + int ret; + u32 i; + + const u32 put_device_ids[] = { + J721E_DEV_MCU_RTI0, + J721E_DEV_MCU_RTI1, + }; + + ti_sci = get_ti_sci_handle(); + dev_ops = &ti_sci->ops.dev_ops; + proc_ops = &ti_sci->ops.proc_ops; + + /* Iterate through list of devices to put (shutdown) */ + for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) { + u32 id = put_device_ids[i]; + + ret = dev_ops->put_device(ti_sci, id); + if (ret) + panic("Failed to put device %u (%d)\n", id, ret); + } + + const u32 put_core_ids[] = { + J721E_DEV_MCU_ARMSS0_CPU1, + J721E_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */ + }; + + /* Iterate through list of cores to put (shutdown) */ + for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) { + u32 id = put_core_ids[i]; + + /* + * Queue up the core shutdown request. Note that this call + * needs to be followed up by an actual invocation of an WFE + * or WFI CPU instruction. + */ + ret = proc_ops->proc_shutdown_no_wait(ti_sci, id); + if (ret) + panic("Failed sending core %u shutdown message (%d)\n", + id, ret); + } +} +#endif