From patchwork Wed May 22 18:36:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 1103497 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="e9aB900B"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 458Lyf2nk4z9s9N for ; Thu, 23 May 2019 04:39:38 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 00837C21DCA; Wed, 22 May 2019 18:37:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id C083FC21DD9; Wed, 22 May 2019 18:37:14 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 6F18AC21C4A; Wed, 22 May 2019 18:37:12 +0000 (UTC) Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lists.denx.de (Postfix) with ESMTPS id 82F55C21C4A for ; Wed, 22 May 2019 18:37:11 +0000 (UTC) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x4MIb9m0105804; Wed, 22 May 2019 13:37:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1558550229; bh=hUfKtF736mUIbHGtn9a1o2sXs0W5O35FR3a2kUux060=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=e9aB900B94kFiU7KQwvZi9x9gHu2875zNGmjpVebMZyLSr44w22Q6MBEveT2fLJLO Fn0T94luWvzXzf+0QBNjuTnmDpPV8mBOTvq0CMefFviz3Xx4enI8SbB8Ku0bJqCzvU z1VVdAZhIT3lbq3nEvyGP27J0/S8fAljfLlZ2s8I= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x4MIb9PB103552 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 22 May 2019 13:37:09 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 22 May 2019 13:37:09 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 22 May 2019 13:37:09 -0500 Received: from a0131933.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x4MIb8MW096383; Wed, 22 May 2019 13:37:09 -0500 From: Lokesh Vutla To: Tom Rini , Date: Wed, 22 May 2019 13:36:56 -0500 Message-ID: <20190522183707.19326-4-lokeshvutla@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190522183707.19326-1-lokeshvutla@ti.com> References: <20190522183707.19326-1-lokeshvutla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Tero Kristo Subject: [U-Boot] [PATCH 03/14] armV7R: K3: j721e: Allow using SPL BSS pre-relocation X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Andreas Dannenberg In order to be able to use more advanced driver functionality which often relies on having BSS initialized during early boot prior to relocation several things need to be in place: 1) Memory needs to be available for BSS to use. For this, we locate BSS at the top of the MCU SRAM area, with the stack starting right below it, 2) We need to zero-initialize BSS ourselves which will we do during board_init_f(), 3) We would also like to skip the implicit zero-initialization as part of SPL relocation, so that already initialized variables will carry over post-relocation. We will do this with a separate commit by turning on the respective CONFIG option. In this commit we only zero-initialize BSS. Assignment of SP will be done in the environment setup. Signed-off-by: Andreas Dannenberg Signed-off-by: Lokesh Vutla --- arch/arm/mach-k3/j721e_init.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c index d798aed481..6da4cf6d22 100644 --- a/arch/arm/mach-k3/j721e_init.c +++ b/arch/arm/mach-k3/j721e_init.c @@ -24,6 +24,13 @@ void board_init_f(ulong dummy) #ifdef CONFIG_CPU_V7R setup_k3_mpu_regions(); + + /* + * When running SPL on R5 we are using SRAM for BSS to have global + * data etc. working prior to relocation. Since this means we need + * to self-manage BSS, clear that section now. + */ + memset(__bss_start, 0, __bss_end - __bss_start); #endif /* Init DM early */