From patchwork Wed May 22 18:37:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 1103504 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="vzDEIxQ6"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 458M2J2bXMz9s9N for ; Thu, 23 May 2019 04:42:48 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 13338C21E4F; Wed, 22 May 2019 18:39:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6710FC21E31; Wed, 22 May 2019 18:37:18 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 2818AC21C2C; Wed, 22 May 2019 18:37:12 +0000 (UTC) Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lists.denx.de (Postfix) with ESMTPS id F421BC21DB6 for ; Wed, 22 May 2019 18:37:11 +0000 (UTC) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x4MIbAeR070330; Wed, 22 May 2019 13:37:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1558550230; bh=lHfxDzYF7XgvhzxD9GYwfBx0On6Ok20AfH05otvoYgQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=vzDEIxQ6hj6TDEc15q4V3+NVqRX89CAqBBt5zVSYu5sNeiQGSodipo2tsYfHiJBrY wHJsJ2Gz/pmjk9RFz5rvOmFd+Vb+WFOfOjaFD9QhTBIlJFFv98OGDX6tyayfTS8b/X qnZRPzNPDpkEoG7drhM74Zyaj1ZUNnLmZNtBvC5A= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x4MIbAeh103577 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 22 May 2019 13:37:10 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 22 May 2019 13:37:10 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 22 May 2019 13:37:10 -0500 Received: from a0131933.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x4MIb8Mf096383; Wed, 22 May 2019 13:37:10 -0500 From: Lokesh Vutla To: Tom Rini , Date: Wed, 22 May 2019 13:37:05 -0500 Message-ID: <20190522183707.19326-13-lokeshvutla@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190522183707.19326-1-lokeshvutla@ti.com> References: <20190522183707.19326-1-lokeshvutla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Tero Kristo Subject: [U-Boot] [PATCH 12/14] arm: dts: j721e: Add r5 specific dt support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add initial support for dt that runs on r5. Signed-off-by: Lokesh Vutla Signed-off-by: Andreas Dannenberg --- arch/arm/dts/Makefile | 3 +- .../k3-j721e-common-proc-board-u-boot.dtsi | 75 ++++++++++ .../arm/dts/k3-j721e-r5-common-proc-board.dts | 138 ++++++++++++++++++ 3 files changed, 215 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi create mode 100644 arch/arm/dts/k3-j721e-r5-common-proc-board.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 818d66a17a..89a12f6c9f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -750,7 +750,8 @@ dtb-$(CONFIG_TARGET_STM32MP1) += \ stm32mp157c-ev1.dtb dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb -dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb +dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \ + k3-j721e-r5-common-proc-board.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7623n-bananapi-bpi-r2.dtb \ diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi new file mode 100644 index 0000000000..541da22c48 --- /dev/null +++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/ { + chosen { + stdout-path = "serial2:115200n8"; + tick-timer = &timer1; + }; +}; + +&cbass_main{ + u-boot,dm-spl; +}; + +&cbass_mcu_wakeup { + u-boot,dm-spl; + + timer1: timer@40400000 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x40400000 0x0 0x80>; + ti,timer-alwon; + clock-frequency = <25000000>; + u-boot,dm-spl; + }; +}; + +&secure_proxy_main { + u-boot,dm-spl; +}; + +&dmsc { + u-boot,dm-spl; + k3_sysreset: sysreset-controller { + compatible = "ti,sci-sysreset"; + u-boot,dm-spl; + }; +}; + +&k3_pds { + u-boot,dm-spl; +}; + +&k3_clks { + u-boot,dm-spl; +}; + +&k3_reset { + u-boot,dm-spl; +}; + +&wkup_pmx0 { + u-boot,dm-spl; +}; + +&main_pmx0 { + u-boot,dm-spl; +}; + +&main_uart0 { + u-boot,dm-spl; +}; + +&mcu_uart0 { + u-boot,dm-spl; +}; + +&main_sdhci0 { + u-boot,dm-spl; +}; + +&main_sdhci1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts new file mode 100644 index 0000000000..5d8883e2f5 --- /dev/null +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; + +#include "k3-j721e-som-p0.dtsi" + +/ { + aliases { + remoteproc0 = &sysctrler; + remoteproc1 = &a72_0; + }; + + chosen { + stdout-path = "serial2:115200n8"; + tick-timer = &timer1; + }; + + a72_0: a72@0 { + compatible = "ti,am654-rproc"; + reg = <0x0 0x00a90000 0x0 0x10>; + power-domains = <&k3_pds 61>, <&k3_pds 202>; + resets = <&k3_reset 202 0>; + ti,sci = <&dmsc>; + ti,sci-proc-id = <32>; + ti,sci-host-id = <10>; + u-boot,dm-spl; + }; + + clk_200mhz: dummy_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + u-boot,dm-spl; + }; +}; + +&cbass_mcu_wakeup { + mcu_secproxy: secproxy@28380000 { + u-boot,dm-spl; + compatible = "ti,am654-secure-proxy"; + reg = <0x0 0x2a380000 0x0 0x80000>, + <0x0 0x2a400000 0x0 0x80000>, + <0x0 0x2a480000 0x0 0x80000>; + reg-names = "rt", "scfg", "target_data"; + #mbox-cells = <1>; + }; + + sysctrler: sysctrler { + u-boot,dm-spl; + compatible = "ti,am654-system-controller"; + mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>; + mbox-names = "tx", "rx"; + }; +}; + +&dmsc { + mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>; + mbox-names = "tx", "rx", "notify"; + ti,host-id = <4>; + ti,secure-host; +}; + +&wkup_pmx0 { + wkup_uart0_pins_default: wkup_uart0_pins_default { + u-boot,dm-spl; + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ + J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ + >; + }; + + mcu_uart0_pins_default: mcu_uart0_pins_default { + u-boot,dm-spl; + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xe8, PIN_INPUT, 0) /* (H29) WKUP_GPIO0_14.MCU_UART0_CTSn */ + J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */ + J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */ + J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */ + >; + }; +}; + +&main_pmx0 { + main_uart0_pins_default: main_uart0_pins_default { + u-boot,dm-spl; + pinctrl-single,pins = < + J721E_IOPAD(0x1d4, PIN_INPUT, 1) /* (Y3) SPI1_CS0.UART0_CTSn */ + J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */ + J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ + J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ + >; + }; +}; + +&wkup_uart0 { + u-boot,dm-spl; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; + status = "okay"; +}; + +&mcu_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; + status = "okay"; +}; + +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; + status = "okay"; + power-domains = <&k3_pds 146>; +}; + +&main_sdhci0 { + /delete-property/ power-domains; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + clock-names = "clk_xin"; + clocks = <&clk_200mhz>; + ti,driver-strength-ohm = <50>; + non-removable; + bus-width = <8>; +}; + +&main_sdhci1 { + /delete-property/ power-domains; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + clock-names = "clk_xin"; + clocks = <&clk_200mhz>; + ti,driver-strength-ohm = <50>; +}; + +#include "k3-j721e-common-proc-board-u-boot.dtsi"