From patchwork Wed May 22 04:32:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 1103120 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="K5wJiIJE"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4580BK5cJnz9sBV for ; Wed, 22 May 2019 14:33:29 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 5F420C21DEC; Wed, 22 May 2019 04:32:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E5452C21DDC; Wed, 22 May 2019 04:32:30 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id CA983C21D8E; Wed, 22 May 2019 04:32:28 +0000 (UTC) Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lists.denx.de (Postfix) with ESMTPS id 3A11DC21C57 for ; Wed, 22 May 2019 04:32:28 +0000 (UTC) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x4M4WQG6026367; Tue, 21 May 2019 23:32:26 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1558499546; bh=0zyM7Cub4rz48tWpzYEn2uT77KYO4gZiZtT+ZLhBF/Y=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=K5wJiIJESKe5tMhl72sN8EWSgNsGRnwXc9Tx/u+Zii/GhxMHwQJVd6e6so4fySza6 gyNgzZdte3mXNR9hpZN1MGpjAUtdkdVgqHR/GXnK7kuFu9atodoKh3qnnYgKXU6ZSi YyPVDvoaEqE8Dxi4xwhepd9ZaqEcreE0YIoYFAiQ= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x4M4WQvH109716 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 21 May 2019 23:32:26 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 21 May 2019 23:32:26 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 21 May 2019 23:32:26 -0500 Received: from a0131933.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x4M4WP47083051; Tue, 21 May 2019 23:32:26 -0500 From: Lokesh Vutla To: Tom Rini , Date: Tue, 21 May 2019 23:32:20 -0500 Message-ID: <20190522043224.14986-4-lokeshvutla@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190522043224.14986-1-lokeshvutla@ti.com> References: <20190522043224.14986-1-lokeshvutla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Tero Kristo Subject: [U-Boot] [PATCH v2 3/7] armv7R: K3: am654: Shut down R5 core after ATF startup on A53 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Andreas Dannenberg Rather than simply parking the R5 core in WFE after starting up ATF on A53 instead use SYSFW API to properly shut down the R5 CPU cores as well as associated timer resources that were pre-allocated. This allows software further downstream to properly and gracefully bring the R5 cores back online if desired. Signed-off-by: Andreas Dannenberg Signed-off-by: Lokesh Vutla --- arch/arm/mach-k3/am6_init.c | 62 +++++++++++++++++++++++ arch/arm/mach-k3/common.c | 6 ++- arch/arm/mach-k3/include/mach/sys_proto.h | 1 + 3 files changed, 68 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c index 60a580305d..922bd95580 100644 --- a/arch/arm/mach-k3/am6_init.c +++ b/arch/arm/mach-k3/am6_init.c @@ -12,6 +12,7 @@ #include #include "common.h" #include +#include #ifdef CONFIG_SPL_BUILD static void mmr_unlock(u32 base, u32 partition) @@ -185,3 +186,64 @@ void reset_cpu(ulong ignored) { } #endif + +#ifdef CONFIG_SYS_K3_SPL_ATF + +#define AM6_DEV_MCU_RTI0 134 +#define AM6_DEV_MCU_RTI1 135 +#define AM6_DEV_MCU_ARMSS0_CPU0 159 +#define AM6_DEV_MCU_ARMSS0_CPU1 245 + +void release_resources_for_core_shutdown(void) +{ + struct udevice *dev; + struct ti_sci_handle *ti_sci; + struct ti_sci_dev_ops *dev_ops; + struct ti_sci_proc_ops *proc_ops; + int ret; + u32 i; + + const u32 put_device_ids[] = { + AM6_DEV_MCU_RTI0, + AM6_DEV_MCU_RTI1, + }; + + /* Get handle to Device Management and Security Controller (SYSFW) */ + ret = uclass_get_device_by_name(UCLASS_FIRMWARE, "dmsc", &dev); + if (ret) + panic("Failed to get handle to SYSFW (%d)\n", ret); + + ti_sci = (struct ti_sci_handle *)(ti_sci_get_handle_from_sysfw(dev)); + dev_ops = &ti_sci->ops.dev_ops; + proc_ops = &ti_sci->ops.proc_ops; + + /* Iterate through list of devices to put (shutdown) */ + for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) { + u32 id = put_device_ids[i]; + + ret = dev_ops->put_device(ti_sci, id); + if (ret) + panic("Failed to put device %u (%d)\n", id, ret); + } + + const u32 put_core_ids[] = { + AM6_DEV_MCU_ARMSS0_CPU1, + AM6_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */ + }; + + /* Iterate through list of cores to put (shutdown) */ + for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) { + u32 id = put_core_ids[i]; + + /* + * Queue up the core shutdown request. Note that this call + * needs to be followed up by an actual invocation of an WFE + * or WFI CPU instruction. + */ + ret = proc_ops->proc_shutdown_no_wait(ti_sci, id); + if (ret) + panic("Failed sending core %u shutdown message (%d)\n", + id, ret); + } +} +#endif diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 03f01d07ea..ee84d44de8 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -13,6 +13,7 @@ #include #include #include +#include struct ti_sci_handle *get_ti_sci_handle(void) { @@ -51,7 +52,10 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) if (ret) panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret); - debug("ATF started. Waiting indefinitely...\n"); + debug("Releasing resources...\n"); + release_resources_for_core_shutdown(); + + debug("Finalizing core shutdown...\n"); while (1) asm volatile("wfe"); } diff --git a/arch/arm/mach-k3/include/mach/sys_proto.h b/arch/arm/mach-k3/include/mach/sys_proto.h index 018725b4d1..2fa53682ad 100644 --- a/arch/arm/mach-k3/include/mach/sys_proto.h +++ b/arch/arm/mach-k3/include/mach/sys_proto.h @@ -12,4 +12,5 @@ u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr, u32 bound); struct ti_sci_handle *get_ti_sci_handle(void); int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name); +void release_resources_for_core_shutdown(void); #endif