From patchwork Wed May 15 14:15:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sekhar Nori X-Patchwork-Id: 1100090 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="oIheVbJW"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 453xTX3lsvz9sBb for ; Thu, 16 May 2019 00:17:36 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 1B893C21D65; Wed, 15 May 2019 14:15:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 042F6C21BE5; Wed, 15 May 2019 14:15:30 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 24D58C21DB5; Wed, 15 May 2019 14:15:25 +0000 (UTC) Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lists.denx.de (Postfix) with ESMTPS id 42841C21D83 for ; Wed, 15 May 2019 14:15:22 +0000 (UTC) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x4FEFK32052362; Wed, 15 May 2019 09:15:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1557929720; bh=ffdytRtis8/c8Rbmk/QcYoXtXhd8o/3zUfzjeZx1C/Y=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=oIheVbJWqdKgI2pY8cErWRzxkXg5scEntzZAGd4jcprMGbxBCJMkSaqYjyR/MgSZP LnrEJQwHowx6wLEYgfD+VzMHbq+xa3a3T573aBRp6BpO0aphgaoPF4OFMJdWc3W7PI fAhNCFxYA9vPCU1jIIvwADva048c2H0LeN1K2Wps= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x4FEFKA6015740 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 15 May 2019 09:15:20 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 15 May 2019 09:15:19 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 15 May 2019 09:15:19 -0500 Received: from psplinux063.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x4FEF6r7098747; Wed, 15 May 2019 09:15:18 -0500 From: Sekhar Nori To: Tom Rini Date: Wed, 15 May 2019 19:45:04 +0530 Message-ID: <20190515141505.16945-7-nsekhar@ti.com> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20190515141505.16945-1-nsekhar@ti.com> References: <20190515141505.16945-1-nsekhar@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: U-Boot Mailing List Subject: [U-Boot] [PATCH 6/7] arm: dts: k3-am65: add support for PCIe and SERDES X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add needed device-tree nodes to support PCIe 0 and SERDES on AM65x SoC. The nodes are kept disabled by default. Signed-off-by: Sekhar Nori --- arch/arm/dts/k3-am65-main.dtsi | 108 +++++++++++++++++++++++++++++ arch/arm/dts/k3-am65.dtsi | 1 + include/dt-bindings/phy/phy-am654-serdes.h | 13 ++++ 3 files changed, 122 insertions(+) create mode 100644 include/dt-bindings/phy/phy-am654-serdes.h diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi index adcd6341e40c..a564b277c357 100644 --- a/arch/arm/dts/k3-am65-main.dtsi +++ b/arch/arm/dts/k3-am65-main.dtsi @@ -5,6 +5,9 @@ * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ */ +#include +#include + &cbass_main { gic500: interrupt-controller@1800000 { compatible = "arm,gic-v3"; @@ -69,4 +72,109 @@ clock-frequency = <48000000>; current-speed = <115200>; }; + + scm_conf: scm_conf@100000 { + compatible = "syscon", "simple-mfd"; + reg = <0 0x00100000 0 0x1c000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x00100000 0x1c000>; + + serdes_mux: mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */ + <0x4090 0x3>; /* SERDES1 lane select */ + }; + + pcie0_mode: pcie-mode@4060 { + compatible = "syscon"; + reg = <0x00004060 0x4>; + }; + + pcie1_mode: pcie-mode@4070 { + compatible = "syscon"; + reg = <0x00004070 0x4>; + }; + + serdes0_clk: serdes_clk@4080 { + compatible = "syscon"; + reg = <0x00004080 0x4>; + }; + + serdes1_clk: serdes_clk@4090 { + compatible = "syscon"; + reg = <0x00004090 0x4>; + }; + + pcie_devid: pcie-devid@210 { + compatible = "syscon"; + reg = <0x00000210 0x4>; + }; + }; + + serdes0: serdes@900000 { + compatible = "ti,phy-am654-serdes"; + reg = <0x0 0x900000 0x0 0x2000>; + reg-names = "serdes"; + #phy-cells = <2>; + power-domains = <&k3_pds 153>; + clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>; + clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk"; + assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; + assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>; + ti,serdes-clk = <&serdes0_clk>; + mux-controls = <&serdes_mux 0>; + #clock-cells = <1>; + }; + + serdes1: serdes@910000 { + compatible = "ti,phy-am654-serdes"; + reg = <0x0 0x910000 0x0 0x2000>; + reg-names = "serdes"; + #phy-cells = <2>; + power-domains = <&k3_pds 154>; + clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>; + clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk"; + assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>; + assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>; + ti,serdes-clk = <&serdes1_clk>; + mux-controls = <&serdes_mux 1>; + #clock-cells = <1>; + }; + + pcie0_rc: pcie@5500000 { + compatible = "ti,am654-pcie-rc"; + reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>; + reg-names = "app", "dbics", "config", "atu"; + power-domains = <&k3_pds 120>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000 + 0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>; + ti,syscon-pcie-id = <&pcie_devid>; + ti,syscon-pcie-mode = <&pcie0_mode>; + bus-range = <0x0 0xff>; + status = "disabled"; + device_type = "pci"; + num-lanes = <1>; + num-ob-windows = <16>; + num-viewport = <16>; + max-link-speed = <3>; + interrupts = ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, /* INT A */ + <0 0 0 2 &pcie0_intc 0>, /* INT B */ + <0 0 0 3 &pcie0_intc 0>, /* INT C */ + <0 0 0 4 &pcie0_intc 0>; /* INT D */ + msi-map = <0x0 &gic_its 0x0 0x10000>; + + pcie0_intc: legacy-interrupt-controller@1 { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic500>; + interrupts = ; + }; + }; }; diff --git a/arch/arm/dts/k3-am65.dtsi b/arch/arm/dts/k3-am65.dtsi index 3d4bf369d030..b87081765894 100644 --- a/arch/arm/dts/k3-am65.dtsi +++ b/arch/arm/dts/k3-am65.dtsi @@ -61,6 +61,7 @@ <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */ + <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ /* MCUSS Range */ <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, diff --git a/include/dt-bindings/phy/phy-am654-serdes.h b/include/dt-bindings/phy/phy-am654-serdes.h new file mode 100644 index 000000000000..e8d901729ed9 --- /dev/null +++ b/include/dt-bindings/phy/phy-am654-serdes.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for AM654 SERDES. + */ + +#ifndef _DT_BINDINGS_AM654_SERDES +#define _DT_BINDINGS_AM654_SERDES + +#define AM654_SERDES_CMU_REFCLK 0 +#define AM654_SERDES_LO_REFCLK 1 +#define AM654_SERDES_RO_REFCLK 2 + +#endif /* _DT_BINDINGS_AM654_SERDES */