From patchwork Wed Apr 24 05:44:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 1089955 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=aosc.io Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44pq5c4QbTz9s3Z for ; Wed, 24 Apr 2019 15:44:50 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 1E4A6C21E08; Wed, 24 Apr 2019 05:44:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=SPF_HELO_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 85974C21D65; Wed, 24 Apr 2019 05:44:43 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B9A57C21D65; Wed, 24 Apr 2019 05:44:42 +0000 (UTC) Received: from balrog.mythic-beasts.com (balrog.mythic-beasts.com [46.235.227.24]) by lists.denx.de (Postfix) with ESMTPS id 66BF1C21C57 for ; Wed, 24 Apr 2019 05:44:42 +0000 (UTC) Received: from [199.195.250.187] (port=37816 helo=hermes.aosc.io) by balrog.mythic-beasts.com with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1hJAhw-0000h4-Rg; Wed, 24 Apr 2019 06:44:41 +0100 Received: from localhost (localhost [127.0.0.1]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id CB01D3F514; Wed, 24 Apr 2019 05:44:27 +0000 (UTC) From: Icenowy Zheng To: Jagan Teki , Maxime Ripard , Chen-Yu Tsai Date: Wed, 24 Apr 2019 13:44:12 +0800 Message-Id: <20190424054412.58117-1-icenowy@aosc.io> X-BlackCat-Spam-Score: 9 Cc: u-boot@lists.denx.de, linux-sunxi@googlegroups.com, Icenowy Zheng Subject: [U-Boot] [PATCH] sunxi: set PIO voltage to hardware-detected value on startup on H6 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The Allwinner H6 SoC has a register to set the PIO banks' voltage. When it mismatches the real voltage supplied to the VCC to the PIO supply, the PIO will work improperly. The PIO controller also has a register that contains the status of each VCC rail of the PIO supplies, and it has the same definition with the configuration register. so we can just copy the content of this register to the configuration register at startup, to ensure the configuration is correct at startup stage. Signed-off-by: Icenowy Zheng --- arch/arm/include/asm/arch-sunxi/gpio.h | 3 +++ arch/arm/mach-sunxi/board.c | 9 +++++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 40a3f845d0..a646ea6a3c 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -73,6 +73,9 @@ struct sunxi_gpio_reg { struct sunxi_gpio_int gpio_int; }; +#define SUN50I_H6_GPIO_POW_MOD_SEL 0x340 +#define SUN50I_H6_GPIO_POW_MOD_VAL 0x348 + #define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_L) ? \ &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \ &((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_L]) diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index c6dd7b8e54..bd3b5d8303 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -65,6 +65,7 @@ struct mm_region *mem_map = sunxi_mem_map; static int gpio_init(void) { + __maybe__unused uint val; #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F) #if defined(CONFIG_MACH_SUN4I) || \ defined(CONFIG_MACH_SUN7I) || \ @@ -139,6 +140,14 @@ static int gpio_init(void) #error Unsupported console port number. Please fix pin mux settings in board.c #endif +#ifdef CONFIG_MACH_SUN50I_H6 + /* Update PIO power bias configuration by copy hardware detected value */ + val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL); + writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL); + val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL); + writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL); +#endif + return 0; }