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[U-Boot,v3,1/4] arm: socfpga: fix comment about SPL memory layout

Message ID 20190328200719.31274-2-simon.k.r.goldschmidt@gmail.com
State Superseded, archived
Delegated to: Marek Vasut
Headers show
Series arm: socfpga: stack and Kconfig cleanups | expand

Commit Message

Simon Goldschmidt March 28, 2019, 8:07 p.m. UTC 
The comment about SPL memory layout for socfpga gen5 is outdated: the
initial malloc memory is now at the end of the SRAM, gd is below it
(see board_init_f_alloc_reserve).

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---

Changes in v3: None
Changes in v2: None

 include/configs/socfpga_common.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
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Patch

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 24f8665c24..0c480fe4a4 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -236,9 +236,9 @@  unsigned int cm_get_qspi_controller_clk_hz(void);
  *
  * 0xFFFF_0000 ...... Start of SRAM
  * 0xFFFF_xxxx ...... Top of stack (grows down)
- * 0xFFFF_yyyy ...... Malloc area
- * 0xFFFF_zzzz ...... Global Data
- * 0xFFFF_FF00 ...... End of SRAM
+ * 0xFFFF_yyyy ...... Global Data
+ * 0xFFFF_zzzz ...... Malloc area
+ * 0xFFFF_FFFF ...... End of SRAM
  *
  * SRAM Memory layout for Arria 10:
  * 0xFFE0_0000 ...... Start of SRAM (bottom)