From patchwork Mon Mar 11 08:20:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1054208 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="lG6wHsAi"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44HrdP1hC7z9s4V for ; Mon, 11 Mar 2019 19:20:25 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id DA93BC21E39; Mon, 11 Mar 2019 08:20:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 53365C21C8B; Mon, 11 Mar 2019 08:20:19 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 563D2C21C8B; Mon, 11 Mar 2019 08:20:17 +0000 (UTC) Received: from mail-pf1-f196.google.com (mail-pf1-f196.google.com [209.85.210.196]) by lists.denx.de (Postfix) with ESMTPS id 977F8C21C3F for ; Mon, 11 Mar 2019 08:20:16 +0000 (UTC) Received: by mail-pf1-f196.google.com with SMTP id n22so3164116pfa.3 for ; Mon, 11 Mar 2019 01:20:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=+Ez9B4MFQMDylO3fRDKbGu6TdI2LwDKhZbEeiLwUsW4=; b=lG6wHsAi9Xw055j0sr9C1N2UDTWDfwN0aLL1p9wvZCfgu8KT204kTuKXvrFbqdrGFb FPiumkXVtC1S8xq+fFX9hc8v9C4mAQ0hEN0bskwFU05UG5njUipA8/O+vacN1eFH/Mav x5Dv82XjIZr+Ze0FsrmVQjTLTs3GyiwH7CBSU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=+Ez9B4MFQMDylO3fRDKbGu6TdI2LwDKhZbEeiLwUsW4=; b=euWydOAO1lzo84LzjlIPqQAsLqnlv31r+Llnoft1Ot9Qquz8jCtPelig0G5KS7485z wvfUBJjKTAWfCGemyyRWEJtAC4h8xUxkDGWm38FJhOC34HFaVwlTDPc1brzPTeBnzu0m Ai9DTovaE12pcoB7qTmvzhZGqy6aVNjLtO7kHfwf5Ht89XkyBrFHOT/ASGFv2zoQ0ME+ 4rCg+2Gcrwyd9dKl1FOBnVTuENjRjHcb87WLbJIPiGsZy0GKtUPXQqphYlwz+wCMvvwD OfmVinDg25TIwQTYZEsn5hPL/uIrXuG2GC+10U7CjFSp66OM+8PmKf9t9A/LlfNezQYV ZH7w== X-Gm-Message-State: APjAAAVodPM9yeyomIHiKZ3y6+20SFEO+nbtEECCTnz1qPm8Y2ILBRBQ 9aBHL7DjKyoKj0NsRKCka+RIvg== X-Google-Smtp-Source: APXvYqxpaaguz4N8Rs3zfnaHLWt4lCPfj9bZGg9aL/sY8LJ67m8+CJAFiSdfMvhiZ2VcAhEIZUNkUw== X-Received: by 2002:a63:2259:: with SMTP id t25mr17070795pgm.107.1552292415127; Mon, 11 Mar 2019 01:20:15 -0700 (PDT) Received: from localhost.localdomain ([115.97.184.151]) by smtp.gmail.com with ESMTPSA id l5sm8262196pfi.97.2019.03.11.01.20.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Mar 2019 01:20:14 -0700 (PDT) From: Jagan Teki To: Simon Glass , Philipp Tomsich Date: Mon, 11 Mar 2019 13:50:02 +0530 Message-Id: <20190311082005.18550-1-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 MIME-Version: 1.0 Cc: u-boot@lists.denx.de, zhaoyifan , linux-amarula@amarulasolutions.com, Akash Gajjar Subject: [U-Boot] [PATCH 1/4] rockchip: dts: rk3399: Sync rk3399-opp from Linux X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Sync rk3399-opp.dtsi from Linux. Linux commit details about the rk3399-opp.dtsi sync: "arm64: dts: rockchip: use SPDX-License-Identifier" (sha1: 4ee99cebd486238ac433da823b95cc5f8d8a6905) Signed-off-by: Jagan Teki Reviewed-by: Philipp Tomsich --- arch/arm/dts/rk3399-opp.dtsi | 133 +++++++++++++++++++++++++++++++++++ 1 file changed, 133 insertions(+) create mode 100644 arch/arm/dts/rk3399-opp.dtsi diff --git a/arch/arm/dts/rk3399-opp.dtsi b/arch/arm/dts/rk3399-opp.dtsi new file mode 100644 index 0000000000..d6f1095abb --- /dev/null +++ b/arch/arm/dts/rk3399-opp.dtsi @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd + */ + +/ { + cluster0_opp: opp-table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <800000>; + clock-latency-ns = <40000>; + }; + opp01 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <800000>; + }; + opp02 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <850000>; + }; + opp03 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <925000>; + }; + opp04 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1000000>; + }; + opp05 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1125000>; + }; + }; + + cluster1_opp: opp-table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <800000>; + clock-latency-ns = <40000>; + }; + opp01 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <800000>; + }; + opp02 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <825000>; + }; + opp03 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <875000>; + }; + opp04 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <950000>; + }; + opp05 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1025000>; + }; + opp06 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <1100000>; + }; + opp07 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1200000>; + }; + }; + + gpu_opp_table: opp-table2 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <800000>; + }; + opp01 { + opp-hz = /bits/ 64 <297000000>; + opp-microvolt = <800000>; + }; + opp02 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <825000>; + }; + opp03 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <875000>; + }; + opp04 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <925000>; + }; + opp05 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1100000>; + }; + }; +}; + +&cpu_l0 { + operating-points-v2 = <&cluster0_opp>; +}; + +&cpu_l1 { + operating-points-v2 = <&cluster0_opp>; +}; + +&cpu_l2 { + operating-points-v2 = <&cluster0_opp>; +}; + +&cpu_l3 { + operating-points-v2 = <&cluster0_opp>; +}; + +&cpu_b0 { + operating-points-v2 = <&cluster1_opp>; +}; + +&cpu_b1 { + operating-points-v2 = <&cluster1_opp>; +}; + +&gpu { + operating-points-v2 = <&gpu_opp_table>; +};