diff mbox series

[U-Boot,v11,1/9] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10

Message ID 20190305162310.1396-2-tien.fong.chee@intel.com
State Superseded
Delegated to: Marek Vasut
Headers show
Series Add support for loading FPGA bitstream | expand

Commit Message

Chee, Tien Fong March 5, 2019, 4:23 p.m. UTC 
From: Tien Fong Chee <tien.fong.chee@intel.com>

This patch adds description on properties about file name used for both
peripheral bitstream and core bitstream.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>

---

changes for v8
- Removed explanation about support for altr,bitstream-core

changes for v7
- Provided example of setting FPGA FIT image for both early IO release
  and full release FPGA configuration.
---
 .../fpga/altera-socfpga-a10-fpga-mgr.txt           | 26 +++++++++++++++++++++-
 1 file changed, 25 insertions(+), 1 deletion(-)

Comments

Dinh Nguyen March 5, 2019, 7:12 p.m. UTC | #1 
Curious, you sent out 3 versions(2x v10, and v11) within ~2 hours. What
versions should we be reviewing?

On 3/5/19 10:23 AM, tien.fong.chee@intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> This patch adds description on properties about file name used for both
> peripheral bitstream and core bitstream.
> 
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>
Chee, Tien Fong March 7, 2019, 7:51 a.m. UTC | #2 
On Tue, 2019-03-05 at 13:12 -0600, Dinh Nguyen wrote:
> Curious, you sent out 3 versions(2x v10, and v11) within ~2 hours.
> What
> versions should we be reviewing?
2nd version of v10 was resent quickly after request from Dalon to
change the node names. I have comment on the 1st version v10 cover
letter to void the whole series since no review starting yet.

After that, Marek told me to resend in v11.

Sorry for any confusion, please help to review v11, this series of
patches mainly resolved some comments from Simek on [v9]: https://www.m
ail-archive.com/u-boot@lists.denx.de/msg316086.html and node names
changed on patch [2/9]
> 
> On 3/5/19 10:23 AM, tien.fong.chee@intel.com wrote:
> > 
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > 
> > This patch adds description on properties about file name used for
> > both
> > peripheral bitstream and core bitstream.
> > 
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> >
Marek Vasut March 7, 2019, 8:18 a.m. UTC | #3 
On 3/7/19 8:51 AM, Chee, Tien Fong wrote:
> On Tue, 2019-03-05 at 13:12 -0600, Dinh Nguyen wrote:
>> Curious, you sent out 3 versions(2x v10, and v11) within ~2 hours.
>> What
>> versions should we be reviewing?
> 2nd version of v10 was resent quickly after request from Dalon to
> change the node names. I have comment on the 1st version v10 cover
> letter to void the whole series since no review starting yet.
> 
> After that, Marek told me to resend in v11.

That is not true, I merely asked whether the v10 that was reposted is
actually v11 .

> Sorry for any confusion, please help to review v11, this series of
> patches mainly resolved some comments from Simek on [v9]: https://www.m
> ail-archive.com/u-boot@lists.denx.de/msg316086.html and node names
> changed on patch [2/9]
>>
>> On 3/5/19 10:23 AM, tien.fong.chee@intel.com wrote:
>>>
>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>
>>> This patch adds description on properties about file name used for
>>> both
>>> peripheral bitstream and core bitstream.
>>>
>>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Chee, Tien Fong March 7, 2019, 8:30 a.m. UTC | #4 
On Thu, 2019-03-07 at 09:18 +0100, Marek Vasut wrote:
> On 3/7/19 8:51 AM, Chee, Tien Fong wrote:
> > 
> > On Tue, 2019-03-05 at 13:12 -0600, Dinh Nguyen wrote:
> > > 
> > > Curious, you sent out 3 versions(2x v10, and v11) within ~2
> > > hours.
> > > What
> > > versions should we be reviewing?
> > 2nd version of v10 was resent quickly after request from Dalon to
> > change the node names. I have comment on the 1st version v10 cover
> > letter to void the whole series since no review starting yet.
> > 
> > After that, Marek told me to resend in v11.
> That is not true, I merely asked whether the v10 that was reposted is
> actually v11 .
Ohh...sorry for misunderstanding, i thought you was asking me to resend
v11 if there are any changes on v10.
> 
> > 
> > Sorry for any confusion, please help to review v11, this series of
> > patches mainly resolved some comments from Simek on [v9]: https://w
> > ww.m
> > ail-archive.com/u-boot@lists.denx.de/msg316086.html and node names
> > changed on patch [2/9]
> > > 
> > > 
> > > On 3/5/19 10:23 AM, tien.fong.chee@intel.com wrote:
> > > > 
> > > > 
> > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > 
> > > > This patch adds description on properties about file name used
> > > > for
> > > > both
> > > > peripheral bitstream and core bitstream.
> > > > 
> > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>
Marek Vasut March 7, 2019, 8:38 a.m. UTC | #5 
On 3/7/19 9:30 AM, Chee, Tien Fong wrote:
> On Thu, 2019-03-07 at 09:18 +0100, Marek Vasut wrote:
>> On 3/7/19 8:51 AM, Chee, Tien Fong wrote:
>>>
>>> On Tue, 2019-03-05 at 13:12 -0600, Dinh Nguyen wrote:
>>>>
>>>> Curious, you sent out 3 versions(2x v10, and v11) within ~2
>>>> hours.
>>>> What
>>>> versions should we be reviewing?
>>> 2nd version of v10 was resent quickly after request from Dalon to
>>> change the node names. I have comment on the 1st version v10 cover
>>> letter to void the whole series since no review starting yet.
>>>
>>> After that, Marek told me to resend in v11.
>> That is not true, I merely asked whether the v10 that was reposted is
>> actually v11 .
> Ohh...sorry for misunderstanding, i thought you was asking me to resend
> v11 if there are any changes on v10.

If you refer to "Is this actually V11 ?" , then no, I was asking whether
this V10 repost was actually a V11 , whether there were changes between
those two versions of V10. Based on the discussion, I think there were some.
Chee, Tien Fong March 7, 2019, 8:56 a.m. UTC | #6 
On Thu, 2019-03-07 at 09:38 +0100, Marek Vasut wrote:
> On 3/7/19 9:30 AM, Chee, Tien Fong wrote:
> > 
> > On Thu, 2019-03-07 at 09:18 +0100, Marek Vasut wrote:
> > > 
> > > On 3/7/19 8:51 AM, Chee, Tien Fong wrote:
> > > > 
> > > > 
> > > > On Tue, 2019-03-05 at 13:12 -0600, Dinh Nguyen wrote:
> > > > > 
> > > > > 
> > > > > Curious, you sent out 3 versions(2x v10, and v11) within ~2
> > > > > hours.
> > > > > What
> > > > > versions should we be reviewing?
> > > > 2nd version of v10 was resent quickly after request from Dalon
> > > > to
> > > > change the node names. I have comment on the 1st version v10
> > > > cover
> > > > letter to void the whole series since no review starting yet.
> > > > 
> > > > After that, Marek told me to resend in v11.
> > > That is not true, I merely asked whether the v10 that was
> > > reposted is
> > > actually v11 .
> > Ohh...sorry for misunderstanding, i thought you was asking me to
> > resend
> > v11 if there are any changes on v10.
> If you refer to "Is this actually V11 ?" , then no, I was asking
> whether
> this V10 repost was actually a V11 , whether there were changes
> between
> those two versions of V10. Based on the discussion, I think there
> were some.
Yeah, the repost was actually 2nd verison of V10, with minor changed on
node names for patch [2/9].
>
diff mbox series

Patch

diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
index 2fd8e7a847..da210bfc86 100644
--- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
+++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
@@ -7,8 +7,31 @@  Required properties:
                - The second index is for writing FPGA configuration data.
 - resets     : Phandle and reset specifier for the device's reset.
 - clocks     : Clocks used by the device.
+- altr,bitstream : Fit image file name for both FPGA peripheral bitstream,
+		   FPGA core bitstream and full bitstream.
 
-Example:
+		   Full bitstream, consist of peripheral bitstream and core
+		   bitstream.
+
+		   FPGA peripheral bitstream is used to initialize FPGA IOs,
+		   PLL, IO48 and DDR. This bitstream is required to get DDR up
+		   running.
+
+		   FPGA core bitstream contains FPGA design which is used to
+		   program FPGA CRAM and ERAM.
+
+Example: Bundles both peripheral bitstream and core bitstream into FIT image
+	 called fit_spl_fpga.itb. This FIT image can be created through running
+	 this command: tools/mkimage
+		       -E -p 400
+		       -f board/altera/arria10-socdk/fit_spl_fpga.its
+		       fit_spl_fpga.itb
+
+	 For details of describing structure and contents of the FIT image,
+	 please refer board/altera/arria10-socdk/fit_spl_fpga.its
+
+- Examples for booting with full release or booting with early IO release, then
+  follow by entering early user mode:
 
 	fpga_mgr: fpga-mgr@ffd03000 {
 		compatible = "altr,socfpga-a10-fpga-mgr";
@@ -16,4 +39,5 @@  Example:
 		       0xffcfe400 0x20>;
 		clocks = <&l4_mp_clk>;
 		resets = <&rst FPGAMGR_RESET>;
+		altr,bitstream = "fit_spl_fpga.itb";
 	};