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[U-Boot,v2,5/5] arm: socfpga: gen5: reduce SPL pre-reloc malloc

Message ID 20190304205352.13159-6-simon.k.r.goldschmidt@gmail.com
State Superseded, archived
Delegated to: Marek Vasut
Headers show
Series arm: socfpga: stack and Kconfig cleanups | expand

Commit Message

Simon Goldschmidt March 4, 2019, 8:53 p.m. UTC 
By enabling debug prints in malloc_simple, we can see that SPL for socfpga
gen5 does by far not need the 8 KiB malloc pool currently allocated for
SPL in pre-reloc phase.

On socfpga_socrates, 1304 bytes are currently used (and this increases by
~200 bytes only for the sdram/reset fixes in socfpga-next).

To prevent wasting precious SRAM space, let's reduce the initial heap used
for SPL to 2 KiB. This is still some hundred bytes more than currently
used. Also, the gen5 SPL enables stack and heap in DDR memory pretty
early. Only the initial uclass/dm parsing, serial console and DDR
initialization is done in the initial heap, so these 2 KiB should be
enough for all boards.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---

Changes in v2:
- added patch to reduce gen5 SPL initial malloc pool to 2 KiB

 arch/arm/mach-socfpga/Kconfig | 1 +
 1 file changed, 1 insertion(+)
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Patch

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index da801eb660..38d7799881 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -8,6 +8,7 @@  config SPL_STACK_R_ADDR
 
 config SPL_SYS_MALLOC_F_LEN
 	default 0x10000 if TARGET_SOCFPGA_ARRIA10
+	default 0x800 if TARGET_SOCFPGA_GEN5
 
 config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
 	default 0xa2