From patchwork Tue Feb 26 20:31:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Goldschmidt X-Patchwork-Id: 1048552 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Cs4n3d0l"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4489Zs4jdjz9s7T for ; Wed, 27 Feb 2019 07:36:37 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 59A91C21E9F; Tue, 26 Feb 2019 20:34:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id ACA04C21EB1; Tue, 26 Feb 2019 20:32:36 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4C2EEC21F16; Tue, 26 Feb 2019 20:32:25 +0000 (UTC) Received: from mail-wr1-f65.google.com (mail-wr1-f65.google.com [209.85.221.65]) by lists.denx.de (Postfix) with ESMTPS id 6E145C21EEB for ; Tue, 26 Feb 2019 20:32:21 +0000 (UTC) Received: by mail-wr1-f65.google.com with SMTP id d17so15408331wre.10 for ; Tue, 26 Feb 2019 12:32:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=giA+mDGoPQRu44K0Cfo52yNmZTn4xUWj39DmiC2a8oE=; b=Cs4n3d0lq6JWiqVAyLvgtRL5NZJDSU1Hb7E/CZvRdIAxaN6KaoSxJsEjpVgIFYyWmX W+S/vCdjGyokGt2nem96KzxoDQzRCjqckl7WPoMX97SUB4h8IqPS6E0yho6q5lyNdWeF IpGEaowGMHPQbiNPrE+3MS7q62PAXiA1M0rdwcRCMPpYMD1QATJaM9z9o2BCFbcMNJQ8 E1VfehFMWUhvjpoOpHVZeQFQNaxD+nrk95H8GZsVN4WUMXhjW0o9iULnhhAP3XG+UmjJ kFbVWIs4e3kiJnAAZYI85IUZ8ceefnrYNizQFtgJ81/RuS93RdyrlL2vDzOS3jvvhX2S HE6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=giA+mDGoPQRu44K0Cfo52yNmZTn4xUWj39DmiC2a8oE=; b=RjUmSGRTKfKA9A8/uFr5o4ZVPxTLDdffpw58tro3XdkH17wfWnCCW59vL3QJhPa/Fg yeQD+58sOLeqiP7bfrQGynTG0d95egUD0JdcO4j/DnP/DlUYLDZR8DoBLiCkzd43Yxod YWRLTGsGrsIFHC6q97MknAXjQVFHUtVTQsQx0eMzKdysjm8gFfuj6PMZR4nZ6p/24tDt 1CYi+RYXE2PHNp786rdj0BLoKwbhhVoI5QeZTkWwCfzKEYuSVxjlHH+hjFlPHmUGYm9n Rj0oiCorcXIaJ0Q7CGAqTcEY5bAu8Y18/KofU8mQIQiAp/tz4v3faOzsZafDx6Y1Tw4l qm8A== X-Gm-Message-State: AHQUAubhjRJpqBufqwi8bRHbDE2UT3ccAhP0YIOLASxFYu3p+/WEpMB+ 1NZnyRyR20X7Tm6zE1yHah8= X-Google-Smtp-Source: AHgI3Ib6RsTI60jR+pnWVPpPk36QBqqkF7Iz4t1CVL6LqJpjyOvwYZzISswDPPywSK6DviXtux8xkA== X-Received: by 2002:adf:e385:: with SMTP id e5mr7187917wrm.267.1551213141160; Tue, 26 Feb 2019 12:32:21 -0800 (PST) Received: from ubuntu.home ([2a02:8071:6a3:700:9065:254c:ff38:3288]) by smtp.gmail.com with ESMTPSA id x17sm21467423wrd.95.2019.02.26.12.32.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 26 Feb 2019 12:32:19 -0800 (PST) From: Simon Goldschmidt To: Marek Vasut , u-boot@lists.denx.de Date: Tue, 26 Feb 2019 21:31:56 +0100 Message-Id: <20190226203156.6404-9-simon.k.r.goldschmidt@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190226203156.6404-1-simon.k.r.goldschmidt@gmail.com> References: <20190226203156.6404-1-simon.k.r.goldschmidt@gmail.com> Cc: Tom Rini Subject: [U-Boot] [PATCH v3 8/8] arm: socfpga: implement proper peripheral reset X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This commit removes ad-hoc reset handling for peripheral resets from SPL for socfpga gen5. This is done because as U-Boot drivers support reset handling by now. Signed-off-by: Simon Goldschmidt --- Changes in v3: - keep the call to enable fpga bridges in SPL Changes in v2: - removed Kconfig option OLD_SOCFPGA_KERNEL_COMPAT since compatibility now uses an environment variable arch/arm/mach-socfpga/misc_gen5.c | 10 ---------- arch/arm/mach-socfpga/spl_gen5.c | 9 +-------- 2 files changed, 1 insertion(+), 18 deletions(-) diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 6e11ba6cb2..9865f5b5b1 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -201,16 +201,6 @@ int arch_early_init_r(void) /* Add device descriptor to FPGA device table */ socfpga_fpga_add(&altera_fpga[0]); -#ifdef CONFIG_DESIGNWARE_SPI - /* Get Designware SPI controller out of reset */ - socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0); - socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0); -#endif - -#ifdef CONFIG_NAND_DENALI - socfpga_per_reset(SOCFPGA_RESET(NAND), 0); -#endif - return 0; } diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index 1bff8cbfcf..552eaf6864 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -36,16 +36,12 @@ u32 spl_boot_device(void) return BOOT_DEVICE_RAM; case 0x2: /* NAND Flash (1.8V) */ case 0x3: /* NAND Flash (3.0V) */ - socfpga_per_reset(SOCFPGA_RESET(NAND), 0); return BOOT_DEVICE_NAND; case 0x4: /* SD/MMC External Transceiver (1.8V) */ case 0x5: /* SD/MMC Internal Transceiver (3.0V) */ - socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0); - socfpga_per_reset(SOCFPGA_RESET(DMA), 0); return BOOT_DEVICE_MMC1; case 0x6: /* QSPI Flash (1.8V) */ case 0x7: /* QSPI Flash (3.0V) */ - socfpga_per_reset(SOCFPGA_RESET(QSPI), 0); return BOOT_DEVICE_SPI; default: printf("Invalid boot device (bsel=%08x)!\n", bsel); @@ -99,9 +95,7 @@ void board_init_f(ulong dummy) socfpga_bridges_reset(1); } - socfpga_per_reset(SOCFPGA_RESET(UART0), 0); socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0); - timer_init(); debug("Reconfigure Clock Manager\n"); @@ -123,8 +117,7 @@ void board_init_f(ulong dummy) sysmgr_pinmux_init(); sysmgr_config_warmrstcfgio(0); - /* De-assert reset for peripherals and bridges based on handoff */ - reset_deassert_peripherals_handoff(); + /* De-assert reset for bridges based on handoff */ socfpga_bridges_reset(0); debug("Unfreezing/Thaw all I/O banks\n");