From patchwork Mon Feb 25 20:27:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Murali Karicheri X-Patchwork-Id: 1047978 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="XXrx7bsx"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 447YQG5Mvrz9s4Z for ; Tue, 26 Feb 2019 07:27:02 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 657E1C21D9A; Mon, 25 Feb 2019 20:26:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id BEE4DC21D8A; Mon, 25 Feb 2019 20:25:42 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 26C7BC21C57; Mon, 25 Feb 2019 20:25:41 +0000 (UTC) Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lists.denx.de (Postfix) with ESMTPS id 7DCE6C21BE5 for ; Mon, 25 Feb 2019 20:25:40 +0000 (UTC) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x1PKPYx6025107; Mon, 25 Feb 2019 14:25:34 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1551126334; bh=tcAkMNVqC2rq2dNazW9d0iE8azi3DA1vXCCJGOyL8pQ=; h=From:To:Subject:Date:In-Reply-To:References; b=XXrx7bsx2NBqYuYssXN3dqB4bGWmC4UNC2Crby+S+vcdTyuYaIm4xaH2pU7lkK31V yDRzsAiFkKia9AVxwjhAhcFkvGKqOo9th+OAIQZP26VzR2OjdKOY8BEdL6TIaoJUzq +0Nbq5ann1ldDKmDFx5YGl+RalztdbMYpRoz79fs= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x1PKPYrg004864 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Feb 2019 14:25:34 -0600 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 25 Feb 2019 14:25:34 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 25 Feb 2019 14:25:33 -0600 Received: from uda0868495.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x1PKPWi4014658; Mon, 25 Feb 2019 14:25:33 -0600 From: Murali Karicheri To: , , , , , , , Date: Mon, 25 Feb 2019 15:27:34 -0500 Message-ID: <20190225202739.26916-3-m-karicheri2@ti.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20190225202739.26916-1-m-karicheri2@ti.com> References: <20190225202739.26916-1-m-karicheri2@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Subject: [U-Boot] [PATCH v4 2/7] ARM: k2g-ice: Add pinmux support for rgmii interface X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This add pinmux configuration for rgmii interface so that network driver can be supported on K2G ICE boards. The pinmux configurations for this are generated using the pinmux tool at https://dev.ti.com/pinmux/app.html#/default As this required some BUFFER_CLASS definitions, same is re-used from the linux defnitions in include/dt-bindings/pinctrl/keystone.h Signed-off-by: Murali Karicheri Reviewed-by: Lokesh Vutla Acked-by: Joe Hershberger --- arch/arm/mach-keystone/include/mach/mux-k2g.h | 5 +++++ board/ti/ks2_evm/mux-k2g.h | 19 +++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/arch/arm/mach-keystone/include/mach/mux-k2g.h b/arch/arm/mach-keystone/include/mach/mux-k2g.h index 809b72d5bf..67d47f8172 100644 --- a/arch/arm/mach-keystone/include/mach/mux-k2g.h +++ b/arch/arm/mach-keystone/include/mach/mux-k2g.h @@ -27,6 +27,11 @@ #define PIN_PTU (1 << 17) /* pull up */ #define PIN_PTD (0 << 17) /* pull down */ +#define BUFFER_CLASS_B (0 << 19) +#define BUFFER_CLASS_C (1 << 19) +#define BUFFER_CLASS_D (2 << 19) +#define BUFFER_CLASS_E (3 << 19) + #define MODE(m) ((m) & 0x7) #define MAX_PIN_N 260 diff --git a/board/ti/ks2_evm/mux-k2g.h b/board/ti/ks2_evm/mux-k2g.h index ea23b886f9..6aa785ea42 100644 --- a/board/ti/ks2_evm/mux-k2g.h +++ b/board/ti/ks2_evm/mux-k2g.h @@ -348,6 +348,25 @@ struct pin_cfg k2g_ice_evm_pin_cfg[] = { { 133, MODE(0) }, /* SOC_QSPI_D2 */ { 134, MODE(0) }, /* SOC_QSPI_D3 */ { 135, MODE(0) }, /* SOC_QSPI_CSN0 */ + + /* EMAC */ + { 72, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXC */ + { 77, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD3 */ + { 78, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD2 */ + { 79, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD1 */ + { 80, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD0 */ + { 81, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXCTL */ + { 85, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXC */ + { 91, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD3 */ + { 92, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD2 */ + { 93, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD1 */ + { 94, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD0 */ + { 95, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXCTL */ + + /* MDIO */ + { 98, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_DATA */ + { 99, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_CLK */ + { MAX_PIN_N, } };