From patchwork Thu Feb 21 21:43:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Goldschmidt X-Patchwork-Id: 1046463 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="vC1Rh/0m"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4457KM1R8bz9s71 for ; Fri, 22 Feb 2019 08:44:23 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id CAD91C21EC9; Thu, 21 Feb 2019 21:44:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id C4CE8C21E50; Thu, 21 Feb 2019 21:43:45 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id AA97EC21E42; Thu, 21 Feb 2019 21:43:42 +0000 (UTC) Received: from mail-wm1-f67.google.com (mail-wm1-f67.google.com [209.85.128.67]) by lists.denx.de (Postfix) with ESMTPS id DDEFBC21DED for ; Thu, 21 Feb 2019 21:43:41 +0000 (UTC) Received: by mail-wm1-f67.google.com with SMTP id z84so106407wmg.4 for ; Thu, 21 Feb 2019 13:43:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ulpbGmba1rFT4ZcYSHEeO1UokdiU7vloD52TlIzz8XQ=; b=vC1Rh/0mBnTVx1fyLYFh/Uw8NCartN99eOZh4gr1kA1FG89x4UJnfYfhiYnVFxXMbv pT7bQgbMZg8ubHDdva5/yT+PfbXADZr2SgTna3acxTpPOOJXZN9RzrLNEE9lphmUGWOU 9jRmEG6DkRh9aWc3pATMxBmLxIOd7DemcCxnDFquUe0B8RI5fiXjOJO/UyaF47gcR5Q5 vwJIrFgyYxhRvU4oi79qvUE/yef2rZxZQGyy9W0cJ+e/JvneB3qCdqlQy1eDo+Uhe4NJ retDpVhVV64TpIKt6mjJHxztEa29xA8oIKXq2E0X1sYNLaZd5pG66yp9noiEO/pWUR1v N3+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ulpbGmba1rFT4ZcYSHEeO1UokdiU7vloD52TlIzz8XQ=; b=KOabuBWjcR9xoqcsmMQFpZIy+As9eNB5jcvfga6Vr131xzhWniAh7qErUO5m/7Nbxj nwxm58Ga7YmxkeZK6rJ4DsKh8Lp/xqlBtEyl7x7yYaDKUqtEq9WcHBLjOUY5gDFNiwXc dUiGsJZDPnaIFip5ZnLjzGA9i2MePqFTBwljG7mvmNsG0ZsgVh3T/wUwNXebXKYrKbXp ZzfXlUF1rfoJaoUwlhRoEa4o+Wp/nbMMT/CwI9OeoCSbXLPFioqfMzgO4JkQiBtaHgJX Zq1nTaxXNPcNQZZTaqQ3wm6CWX0fB/3PogxvridY7hgUmT/LxDeWgou11ez+IIIQE53B lm0g== X-Gm-Message-State: AHQUAubWa+o/2+BUacV4gXXSXLKhvU6OnEpi4xqMpeGQfye5Eh3lxM2m Ji10WWXN5LYkVbRgmvjYgXc= X-Google-Smtp-Source: AHgI3IZQbwB7/mvsfgfc4IXKa9JmLG8o1L+jyp3WwZd9oPgxEXhsQpivYEdWqIsvitDFihURiSmOrw== X-Received: by 2002:a1c:9c0a:: with SMTP id f10mr343842wme.73.1550785421441; Thu, 21 Feb 2019 13:43:41 -0800 (PST) Received: from ubuntu.home ([2a02:8071:6a3:700:9065:254c:ff38:3288]) by smtp.gmail.com with ESMTPSA id m26sm4308wmg.13.2019.02.21.13.43.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 Feb 2019 13:43:40 -0800 (PST) From: Simon Goldschmidt To: Marek Vasut , u-boot@lists.denx.de Date: Thu, 21 Feb 2019 22:43:26 +0100 Message-Id: <20190221214332.4246-3-simon.k.r.goldschmidt@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190221214332.4246-1-simon.k.r.goldschmidt@gmail.com> References: <20190221214332.4246-1-simon.k.r.goldschmidt@gmail.com> Cc: Tom Rini Subject: [U-Boot] [PATCH v2 2/8] arm: socfpga: gen5: add reset & sdr node to SPL devicetrees X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The SPL for socfpga gen5 currently takes all peripherals out of reset unconditionally. To implement proper reset handling for peripherals, the reset node has to be provided with the SPL dts. In preparation to move the DDR driver to DM, the sdr node is required in SPL, too. This patch adds "u-boot,dm-pre-reloc" to U-Boot specific dtsi addon files so that the reset manager and SDR driver correctly probe in SPL. Signed-off-by: Simon Goldschmidt --- Changes in v2: None arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi | 8 ++++++++ arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts | 8 ++++++++ arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi | 8 ++++++++ arch/arm/dts/socfpga_cyclone5_de10_nano.dts | 8 ++++++++ arch/arm/dts/socfpga_cyclone5_de1_soc.dts | 8 ++++++++ arch/arm/dts/socfpga_cyclone5_is1.dts | 8 ++++++++ arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi | 8 ++++++++ arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi | 8 ++++++++ arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi | 8 ++++++++ arch/arm/dts/socfpga_cyclone5_sr1500.dts | 8 ++++++++ arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi | 8 ++++++++ 11 files changed, 88 insertions(+) diff --git a/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi index c44d1ee2fa..8aaec56285 100644 --- a/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi @@ -17,6 +17,14 @@ }; }; +&rst { + u-boot,dm-pre-reloc; +}; + +&sdr { + u-boot,dm-pre-reloc; +}; + &watchdog0 { status = "disabled"; }; diff --git a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts index a387071674..61907771e0 100644 --- a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts +++ b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts @@ -30,6 +30,14 @@ }; }; +&rst { + u-boot,dm-pre-reloc; +}; + +&sdr { + u-boot,dm-pre-reloc; +}; + &gmac1 { status = "okay"; phy-mode = "rgmii"; diff --git a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi index 08d81da169..00434185f6 100644 --- a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi @@ -16,6 +16,14 @@ }; }; +&rst { + u-boot,dm-pre-reloc; +}; + +&sdr { + u-boot,dm-pre-reloc; +}; + &watchdog0 { status = "disabled"; }; diff --git a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts index e9105743ea..dc84f3de26 100644 --- a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts +++ b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts @@ -32,6 +32,14 @@ }; }; +&rst { + u-boot,dm-pre-reloc; +}; + +&sdr { + u-boot,dm-pre-reloc; +}; + &gmac1 { status = "okay"; phy-mode = "rgmii"; diff --git a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts index 4f076bce93..585d914e30 100644 --- a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts +++ b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts @@ -30,6 +30,14 @@ }; }; +&rst { + u-boot,dm-pre-reloc; +}; + +&sdr { + u-boot,dm-pre-reloc; +}; + &gmac1 { status = "okay"; phy-mode = "rgmii"; diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts b/arch/arm/dts/socfpga_cyclone5_is1.dts index b7054bfd5a..8947128be9 100644 --- a/arch/arm/dts/socfpga_cyclone5_is1.dts +++ b/arch/arm/dts/socfpga_cyclone5_is1.dts @@ -37,6 +37,14 @@ }; }; +&rst { + u-boot,dm-pre-reloc; +}; + +&sdr { + u-boot,dm-pre-reloc; +}; + &gmac1 { status = "okay"; phy-mode = "rgmii"; diff --git a/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi index 9436e0fa8b..13d44072f4 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi @@ -17,6 +17,14 @@ }; }; +&rst { + u-boot,dm-pre-reloc; +}; + +&sdr { + u-boot,dm-pre-reloc; +}; + &can0 { status = "okay"; }; diff --git a/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi index 648f1bd01d..07564a9f13 100644 --- a/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi @@ -17,6 +17,14 @@ }; }; +&rst { + u-boot,dm-pre-reloc; +}; + +&sdr { + u-boot,dm-pre-reloc; +}; + &watchdog0 { status = "disabled"; }; diff --git a/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi index 31bd1dba0f..cf0eb8bb8c 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi @@ -17,6 +17,14 @@ }; }; +&rst { + u-boot,dm-pre-reloc; +}; + +&sdr { + u-boot,dm-pre-reloc; +}; + &watchdog0 { status = "disabled"; }; diff --git a/arch/arm/dts/socfpga_cyclone5_sr1500.dts b/arch/arm/dts/socfpga_cyclone5_sr1500.dts index 6a6c29be79..8a1678ed72 100644 --- a/arch/arm/dts/socfpga_cyclone5_sr1500.dts +++ b/arch/arm/dts/socfpga_cyclone5_sr1500.dts @@ -33,6 +33,14 @@ }; }; +&rst { + u-boot,dm-pre-reloc; +}; + +&sdr { + u-boot,dm-pre-reloc; +}; + &gmac1 { status = "okay"; phy-mode = "rgmii"; diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi index 360b946ba2..90d1fd8858 100644 --- a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi @@ -17,6 +17,14 @@ }; }; +&rst { + u-boot,dm-pre-reloc; +}; + +&sdr { + u-boot,dm-pre-reloc; +}; + &watchdog0 { status = "disabled"; };