From patchwork Thu Feb 21 01:30:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1045701 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 444cRv6BvGz9s5c for ; Thu, 21 Feb 2019 12:33:15 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 8A1FAC220D3; Thu, 21 Feb 2019 01:33:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 633AEC220C6; Thu, 21 Feb 2019 01:32:48 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 32DB9C22095; Thu, 21 Feb 2019 01:32:44 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.101.70]) by lists.denx.de (Postfix) with ESMTP id BF300C21DED for ; Thu, 21 Feb 2019 01:32:43 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EAA4D1596; Wed, 20 Feb 2019 17:32:42 -0800 (PST) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D18A33F575; Wed, 20 Feb 2019 17:32:40 -0800 (PST) From: Andre Przywara To: Maxime Ripard , Jagan Teki Date: Thu, 21 Feb 2019 01:30:26 +0000 Message-Id: <20190221013034.9099-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20190221013034.9099-1-andre.przywara@arm.com> References: <20190221013034.9099-1-andre.przywara@arm.com> Cc: Tom Rini , Alex Graf , u-boot@lists.denx.de, linux-sunxi@googlegroups.com, Icenowy Zheng Subject: [U-Boot] [PATCH 1/9] armv8: Disable exception vectors in SPL by default X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Alexander Graf Commit 1416e2d2253 ("armv8: make SPL exception vectors optional") had a typo in it which effectively disabled exception handling in SPL code always. Since nobody complained, I guess we may as well disable exception handling in SPL always by default. So fix the bug to make the config option effective, but disable exception handling in SPL by default. This gets us to the same functionality as before by default, but with much less code included in the binary. Signed-off-by: Alexander Graf Reviewed-by: Matthias Brugger Reviewed-by: Andre Przywara --- arch/arm/cpu/armv8/Kconfig | 2 +- arch/arm/cpu/armv8/start.S | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 1c12bbde75..fb061c8d73 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -3,7 +3,7 @@ if ARM64 config ARMV8_SPL_EXCEPTION_VECTORS bool "Install crash dump exception vectors" depends on SPL - default y + default n help The default exception vector table is only used for the crash dump, but still takes quite a lot of space in the image size. diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index 12a78ee38b..fe52166e28 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -88,7 +88,7 @@ pie_fixup_done: bl reset_sctrl #endif -#if defined(CONFIG_ARMV8__SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD) .macro set_vbar, regname, reg msr \regname, \reg .endm @@ -354,7 +354,7 @@ ENDPROC(smp_kick_all_cpus) /*-----------------------------------------------------------------------*/ ENTRY(c_runtime_cpu_setup) -#if defined(CONFIG_ARMV8__SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD) /* Relocate vBAR */ adr x0, vectors switch_el x1, 3f, 2f, 1f