From patchwork Fri Feb 15 22:20:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 1043240 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=ziswiler.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 441SfM1qMKz9s3l for ; Sat, 16 Feb 2019 09:31:23 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id E60F7C2210E; Fri, 15 Feb 2019 22:26:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=SPF_HELO_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 3C3C8C220E6; Fri, 15 Feb 2019 22:23:00 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C1A80C21F7D; Fri, 15 Feb 2019 22:21:49 +0000 (UTC) Received: from mout.perfora.net (mout.perfora.net [74.208.4.197]) by lists.denx.de (Postfix) with ESMTPS id CB2E1C21FFB for ; Fri, 15 Feb 2019 22:21:45 +0000 (UTC) Received: from localhost.localdomain ([81.221.138.163]) by mrelay.perfora.net (mreueus001 [74.208.5.2]) with ESMTPSA (Nemesis) id 0MJlT8-1gtfvu0U2G-001ECF; Fri, 15 Feb 2019 23:21:42 +0100 From: Marcel Ziswiler To: u-boot@lists.denx.de Date: Fri, 15 Feb 2019 23:20:37 +0100 Message-Id: <20190215222039.10005-22-marcel@ziswiler.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190215222039.10005-1-marcel@ziswiler.com> References: <20190215222039.10005-1-marcel@ziswiler.com> MIME-Version: 1.0 X-Provags-ID: V03:K1:zIMVVA+V5jRo+S0YuMTf7r8FBxRcBilKUVBXBViUeEwDR78cJLi VKOW+1H9NTLyo0NJ0/Y4L9SEAxpmCnt4GZxHzLv2lw7hw5jbWHcekYOA/LFTyG+n7hxfE0C nEDRgdXF+pHwCzTdvvuF3Y7PpDZrbAj787WAZ0+iDt6ibjNHenY+/hsmTGT1lDiSOsY1toy HBVRkMjkKdQZR00rbx1xA== X-UI-Out-Filterresults: notjunk:1; V03:K0:2nS/eyZfE6A=:9GlzpUeTE6s4S6R8IvtjHJ KKVFAXlAm7yUN8/UfTUcvVY7Rj8plTqKzNfjdmkBgmBaOs5VS5fGFQ1k7rutEMgYsI7KHUh70 0Eu19hZ02d5TpE4drTDaEPXFdn6O8syRiVRXV7ylzWGy4k5011pBHeS5KB2ESJWNEur/rYqSM oVJy6lb2nHHt+uOzJXxFkUk0L/2vY6xjvXNVR+ieEx5/LwpzAlesoHj1GqphfMPE9EWOqe6te vL72HnMRtbnMv0fnmuVOzKS38Unf2tCZ5xiha56XMf93vqOhUyog3rLM/YYLqSEObASzmijwv EWgUK9XSefvtbTII/jPkmjMKA4p+DJnRmWlfUbdg2h6Sgb+8eHpo504DmxFA4HGve3OVc5NIR 316eBfBOGZ1DC4f0oor4y0uWWfECdvjTQS27vmrJuuQt5cMT/s9Cvu+BvOPvi9Q666OGsu/va es/twQx//K7DU7VShi27I2KKRLAaActU9x05cU+qO8I/s9a1FlCUZqcqyuyeGcZj9qY/F6jps wWtZ21fOw9BOhZnMEeYS5ScR7NNmfMJuOccGRMa9c5xlaDD9oXg8bjed19dzibdwxMDPRzKOD pkA+/slBgfmqfomWQPj/T3PbW2ejpu6w4vUnbfnzonREsPBFiBDrOYsIBUYr69lkA5LiyMUP+ l6ePFexQTaNmurDwYip0LQ4l5TvpZqK9lX0BMlOzZWd0Mfp/r/ZVYuieNWz8vjB5Tm8qyderU UmR7RkbKExuswi8u/4BF1ldvEppq3wEHSjzhlw== Cc: Marcel Ziswiler , Stefan Agner Subject: [U-Boot] [PATCH v1 21/22] colibri_vf: use leveling evaluated by DDR validation tools X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Stefan Agner The DDR validation tool (which is part of Processor Expert) allows to evaluate leveling parameters for CR105/CR106/CR110. Several runs have been made with Colibri VF50 and VF61 and it seems to evaluate very similar values. Use this values by default. Note: The newly evaluated parameters seem to require CTLUPD_AREF to be enabled! Note 2: The tool also evaluated 6 as a new value for PHY02/18 GATE_CFG (Coarse adjust of gate open time). However, this seems not to work in practise. Signed-off-by: Stefan Agner Acked-by: Marcel Ziswiler --- board/toradex/colibri_vf/colibri_vf.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index 8c4909af54..87debf1360 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -27,6 +27,13 @@ DECLARE_GLOBAL_DATA_PTR; static struct ddrmc_cr_setting colibri_vf_cr_settings[] = { + { DDRMC_CR79_CTLUPD_AREF(1), 79 }, + /* sets manual values for read lvl. (gate) delay of data slice 0/1 */ + { DDRMC_CR105_RDLVL_DL_0(28), 105 }, + { DDRMC_CR106_RDLVL_GTDL_0(24), 106 }, + { DDRMC_CR110_RDLVL_DL_1(28) | DDRMC_CR110_RDLVL_GTDL_1(24), 110 }, + { DDRMC_CR102_RDLVL_GT_REGEN | DDRMC_CR102_RDLVL_REG_EN, 102 }, + /* AXI */ { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 }, { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },