From patchwork Sat Jan 19 01:30:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1027853 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43hL2y2tSDz9sDB for ; Sat, 19 Jan 2019 12:34:50 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 10FBDC220A6; Sat, 19 Jan 2019 01:33:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 77AC7C2207C; Sat, 19 Jan 2019 01:33:06 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id BB06FC21BE5; Sat, 19 Jan 2019 01:32:51 +0000 (UTC) Received: from foss.arm.com (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by lists.denx.de (Postfix) with ESMTP id 53FC5C220A5 for ; Sat, 19 Jan 2019 01:32:48 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D9CFA15BE; Fri, 18 Jan 2019 17:32:46 -0800 (PST) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CBFC63F6A8; Fri, 18 Jan 2019 17:32:44 -0800 (PST) From: Andre Przywara To: Jagan Teki , Maxime Ripard Date: Sat, 19 Jan 2019 01:30:48 +0000 Message-Id: <20190119013055.28023-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20190119013055.28023-1-andre.przywara@arm.com> References: <20190119013055.28023-1-andre.przywara@arm.com> Cc: Tom Rini , Priit Laes , linux-sunxi@googlegroups.com, u-boot@lists.denx.de, Icenowy Zheng Subject: [U-Boot] [PATCH 2/9] sunxi: clk: A80: add MMC clock support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The A80 handles resets and clock gates for the MMC devices differently, outside of the CCU IP block. Consequently we have a separate clock device with a separate binding for that. Implement that with the respective clock gates and resets to allow the A80 taking part in the DM_MMC game. Signed-off-by: Andre Przywara --- drivers/clk/sunxi/clk_a80.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c index d6dd6a1fa1..2bfc2ca9f5 100644 --- a/drivers/clk/sunxi/clk_a80.c +++ b/drivers/clk/sunxi/clk_a80.c @@ -30,19 +30,45 @@ static const struct ccu_reset a80_resets[] = { [RST_BUS_UART5] = RESET(0x5b4, BIT(21)), }; +static const struct ccu_clk_gate a80_mmc_gates[] = { + [0] = GATE(0x0, BIT(16)), + [1] = GATE(0x4, BIT(16)), + [2] = GATE(0x8, BIT(16)), + [3] = GATE(0xc, BIT(16)), +}; + +static const struct ccu_reset a80_mmc_resets[] = { + [0] = GATE(0x0, BIT(18)), + [1] = GATE(0x4, BIT(18)), + [2] = GATE(0x8, BIT(18)), + [3] = GATE(0xc, BIT(18)), +}; + static const struct ccu_desc a80_ccu_desc = { .gates = a80_gates, .resets = a80_resets, }; +static const struct ccu_desc a80_mmc_clk_desc = { + .gates = a80_mmc_gates, + .resets = a80_mmc_resets, +}; + static int a80_clk_bind(struct udevice *dev) { - return sunxi_reset_bind(dev, ARRAY_SIZE(a80_resets)); + ulong count = ARRAY_SIZE(a80_resets); + + if (device_is_compatible(dev, "allwinner,allwinner,sun9i-a80-mmc")) + count = ARRAY_SIZE(a80_mmc_resets); + + return sunxi_reset_bind(dev, count); } static const struct udevice_id a80_ccu_ids[] = { { .compatible = "allwinner,sun9i-a80-ccu", .data = (ulong)&a80_ccu_desc }, + { .compatible = "allwinner,allwinner,sun9i-a80-mmc", + .data = (ulong)&a80_mmc_clk_desc }, { } };