| Message ID | 20190118111820.71349-11-anup.patel@wdc.com |
|---|---|
| State | Superseded |
| Delegated to: | Andes |
| Headers | show |
| Series | SiFive FU540 Support | expand |
On 18.01.19 12:19, Anup Patel wrote: > From: Atish Patra <atish.patra@wdc.com> > > Currently, timer driver is bound only for hart0. > > There is no mandatory requirement that hart0 should always > come up. In fact, HiFive Unleashed SoC hart0 doesn't boot > in S-mode because it only has M-mode. > > The timer driver should be bound for boot hart. > > Signed-off-by: Atish Patra <atish.patra@wdc.com> ... and here :) > Reviewed-by: Alexander Graf <agraf@suse.de> Alex
> -----Original Message----- > From: Alexander Graf [mailto:agraf@suse.de] > Sent: Friday, January 18, 2019 5:22 PM > To: Anup Patel <Anup.Patel@wdc.com>; Rick Chen <rick@andestech.com>; > Bin Meng <bmeng.cn@gmail.com>; Joe Hershberger > <joe.hershberger@ni.com>; Lukas Auer <lukas.auer@aisec.fraunhofer.de>; > Masahiro Yamada <yamada.masahiro@socionext.com>; Simon Glass > <sjg@chromium.org> > Cc: Palmer Dabbelt <palmer@sifive.com>; Paul Walmsley > <paul.walmsley@sifive.com>; Atish Patra <Atish.Patra@wdc.com>; > Christoph Hellwig <hch@infradead.org>; U-Boot Mailing List <u- > boot@lists.denx.de> > Subject: Re: [PATCH v2 10/11] cpu: Bind timer driver for boot hart > > > > On 18.01.19 12:19, Anup Patel wrote: > > From: Atish Patra <atish.patra@wdc.com> > > > > Currently, timer driver is bound only for hart0. > > > > There is no mandatory requirement that hart0 should always come up. In > > fact, HiFive Unleashed SoC hart0 doesn't boot in S-mode because it > > only has M-mode. > > > > The timer driver should be bound for boot hart. > > > > Signed-off-by: Atish Patra <atish.patra@wdc.com> > > ... and here :) > Sure, I will add my SoB. Regards, Anup
On Fri, 2019-01-18 at 11:19 +0000, Anup Patel wrote: > From: Atish Patra <atish.patra@wdc.com> > > Currently, timer driver is bound only for hart0. > > There is no mandatory requirement that hart0 should always > come up. In fact, HiFive Unleashed SoC hart0 doesn't boot > in S-mode because it only has M-mode. > > The timer driver should be bound for boot hart. > > Signed-off-by: Atish Patra <atish.patra@wdc.com> > Reviewed-by: Alexander Graf <agraf@suse.de> > --- > drivers/cpu/riscv_cpu.c | 7 ++++--- > 1 file changed, 4 insertions(+), 3 deletions(-) > Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
On Fri, Jan 18, 2019 at 7:19 PM Anup Patel <Anup.Patel@wdc.com> wrote: > > From: Atish Patra <atish.patra@wdc.com> > > Currently, timer driver is bound only for hart0. > > There is no mandatory requirement that hart0 should always > come up. In fact, HiFive Unleashed SoC hart0 doesn't boot > in S-mode because it only has M-mode. > > The timer driver should be bound for boot hart. > > Signed-off-by: Atish Patra <atish.patra@wdc.com> > Reviewed-by: Alexander Graf <agraf@suse.de> > --- > drivers/cpu/riscv_cpu.c | 7 ++++--- > 1 file changed, 4 insertions(+), 3 deletions(-) > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c index 5e15df590e..f77c126499 100644 --- a/drivers/cpu/riscv_cpu.c +++ b/drivers/cpu/riscv_cpu.c @@ -10,6 +10,8 @@ #include <dm/device-internal.h> #include <dm/lists.h> +DECLARE_GLOBAL_DATA_PTR; + static int riscv_cpu_get_desc(struct udevice *dev, char *buf, int size) { const char *isa; @@ -62,7 +64,6 @@ static int riscv_cpu_bind(struct udevice *dev) /* save the hart id */ plat->cpu_id = dev_read_addr(dev); - /* first examine the property in current cpu node */ ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq); /* if not found, then look at the parent /cpus node */ @@ -71,7 +72,7 @@ static int riscv_cpu_bind(struct udevice *dev) &plat->timebase_freq); /* - * Bind riscv-timer driver on hart 0 + * Bind riscv-timer driver on boot hart. * * We only instantiate one timer device which is enough for U-Boot. * Pass the "timebase-frequency" value as the driver data for the @@ -80,7 +81,7 @@ static int riscv_cpu_bind(struct udevice *dev) * Return value is not checked since it's possible that the timer * driver is not included. */ - if (!plat->cpu_id && plat->timebase_freq) { + if (plat->cpu_id == gd->arch.boot_hart && plat->timebase_freq) { drv = lists_driver_lookup_name("riscv_timer"); if (!drv) { debug("Cannot find the timer driver, not included?\n");