diff mbox series

[U-Boot,2/3] arm: socfpga: gen5 enable designware_socfpga

Message ID 20190110194954.23950-3-simon.k.r.goldschmidt@gmail.com
State Superseded, archived
Delegated to: Marek Vasut
Headers show
Series arm: socpfpga: gen5 clean up ETH RST & PHY mode | expand

Commit Message

Simon Goldschmidt Jan. 10, 2019, 7:49 p.m. UTC 
Enable the socfpga specific designeware ethernet driver for all Gen5
and Arria10 defconfigs. To make it work, enable REGMAP and SYSCON,
too.

This is required to remove the hacky reset and phy mode handling in
arch/arm/mach-socfpga.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---

 configs/socfpga_arria5_defconfig       | 3 +++
 configs/socfpga_cyclone5_defconfig     | 3 +++
 configs/socfpga_dbm_soc1_defconfig     | 3 +++
 configs/socfpga_de0_nano_soc_defconfig | 3 +++
 configs/socfpga_de10_nano_defconfig    | 3 +++
 configs/socfpga_de1_soc_defconfig      | 3 +++
 configs/socfpga_is1_defconfig          | 3 +++
 configs/socfpga_sockit_defconfig       | 3 +++
 configs/socfpga_socrates_defconfig     | 3 +++
 configs/socfpga_sr1500_defconfig       | 3 +++
 configs/socfpga_vining_fpga_defconfig  | 3 +++
 11 files changed, 33 insertions(+)

Comments

Marek Vasut Jan. 10, 2019, 8:39 p.m. UTC | #1 
On 1/10/19 8:49 PM, Simon Goldschmidt wrote:
> Enable the socfpga specific designeware ethernet driver for all Gen5
> and Arria10 defconfigs. To make it work, enable REGMAP and SYSCON,
> too.
> 
> This is required to remove the hacky reset and phy mode handling in
> arch/arm/mach-socfpga.

Can the Gen5/A10 just "imply" those two options or can the DWMAC driver
"select" those two options in Kconfig ?
Simon Goldschmidt Jan. 10, 2019, 8:43 p.m. UTC | #2 
Am Do., 10. Jan. 2019, 21:40 hat Marek Vasut <marex@denx.de> geschrieben:

> On 1/10/19 8:49 PM, Simon Goldschmidt wrote:
> > Enable the socfpga specific designeware ethernet driver for all Gen5
> > and Arria10 defconfigs. To make it work, enable REGMAP and SYSCON,
> > too.
> >
> > This is required to remove the hacky reset and phy mode handling in
> > arch/arm/mach-socfpga.
>
> Can the Gen5/A10 just "imply" those two options or can the DWMAC driver
> "select" those two options in Kconfig ?
>

Hmm, I'll try that.

Regards,
Simon

>
Marek Vasut Jan. 10, 2019, 8:44 p.m. UTC | #3 
On 1/10/19 9:43 PM, Simon Goldschmidt wrote:
> 
> 
> Am Do., 10. Jan. 2019, 21:40 hat Marek Vasut <marex@denx.de
> <mailto:marex@denx.de>> geschrieben:
> 
>     On 1/10/19 8:49 PM, Simon Goldschmidt wrote:
>     > Enable the socfpga specific designeware ethernet driver for all Gen5
>     > and Arria10 defconfigs. To make it work, enable REGMAP and SYSCON,
>     > too.
>     >
>     > This is required to remove the hacky reset and phy mode handling in
>     > arch/arm/mach-socfpga.
> 
>     Can the Gen5/A10 just "imply" those two options or can the DWMAC driver
>     "select" those two options in Kconfig ?
> 
> 
> Hmm, I'll try that.

And if you get bored, you can imply as much common stuff from the
defconfigs as possible ;-)
diff mbox series

Patch

diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index 0e5e74a621..15cc16b111 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -41,6 +41,8 @@  CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_DFU_MMC=y
 CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
@@ -59,6 +61,7 @@  CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_SOCFPGA=y
 CONFIG_MII=y
 CONFIG_DM_RESET=y
 CONFIG_SPI=y
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index e8de0f5709..2a432d2007 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -41,6 +41,8 @@  CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_DFU_MMC=y
 CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
@@ -60,6 +62,7 @@  CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_SOCFPGA=y
 CONFIG_MII=y
 CONFIG_DM_RESET=y
 CONFIG_SPI=y
diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig
index b6f4f8a3dd..e7726dc3cc 100644
--- a/configs/socfpga_dbm_soc1_defconfig
+++ b/configs/socfpga_dbm_soc1_defconfig
@@ -42,6 +42,8 @@  CONFIG_CMD_FS_GENERIC=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_dbm_soc1"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_DFU_MMC=y
 CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
@@ -54,6 +56,7 @@  CONFIG_MTD_DEVICE=y
 CONFIG_DM_ETH=y
 CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_SOCFPGA=y
 CONFIG_MII=y
 CONFIG_DM_RESET=y
 CONFIG_SPI=y
diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
index 9a89bb5d68..33a412d340 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -41,6 +41,8 @@  CONFIG_CMD_UBI=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_DFU_MMC=y
 CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
@@ -54,6 +56,7 @@  CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_SOCFPGA=y
 CONFIG_MII=y
 CONFIG_DM_RESET=y
 CONFIG_SPI=y
diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig
index db516891ba..662e895af2 100644
--- a/configs/socfpga_de10_nano_defconfig
+++ b/configs/socfpga_de10_nano_defconfig
@@ -37,6 +37,8 @@  CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de10_nano"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_DFU_MMC=y
 CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
@@ -50,6 +52,7 @@  CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_SOCFPGA=y
 CONFIG_MII=y
 CONFIG_DM_RESET=y
 CONFIG_SPI=y
diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig
index 5bed755723..d02bf1c6cf 100644
--- a/configs/socfpga_de1_soc_defconfig
+++ b/configs/socfpga_de1_soc_defconfig
@@ -37,6 +37,8 @@  CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de1_soc"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
@@ -49,6 +51,7 @@  CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_SOCFPGA=y
 CONFIG_MII=y
 CONFIG_DM_RESET=y
 CONFIG_SPI=y
diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig
index 682e58fdb8..97125efae4 100644
--- a/configs/socfpga_is1_defconfig
+++ b/configs/socfpga_is1_defconfig
@@ -38,6 +38,8 @@  CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_is1"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
 CONFIG_FPGA_SOCFPGA=y
@@ -54,6 +56,7 @@  CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_SOCFPGA=y
 CONFIG_MII=y
 CONFIG_DM_RESET=y
 CONFIG_SPI=y
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index abbbcb94d3..a1019d12fc 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -41,6 +41,8 @@  CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_DFU_MMC=y
 CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
@@ -60,6 +62,7 @@  CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_SOCFPGA=y
 CONFIG_MII=y
 CONFIG_DM_RESET=y
 CONFIG_SPI=y
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index 53f8d3c348..4ffce80793 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -42,6 +42,8 @@  CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_DFU_MMC=y
 CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
@@ -60,6 +62,7 @@  CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_SOCFPGA=y
 CONFIG_MII=y
 CONFIG_DM_RESET=y
 CONFIG_SPI=y
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index 97366cdfff..d4720e5580 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -42,6 +42,8 @@  CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
 CONFIG_FPGA_SOCFPGA=y
@@ -60,6 +62,7 @@  CONFIG_PHY_MARVELL=y
 CONFIG_DM_ETH=y
 CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_SOCFPGA=y
 CONFIG_MII=y
 CONFIG_DM_RESET=y
 CONFIG_SPI=y
diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
index 3eba09dcb1..c3d4b815f1 100644
--- a/configs/socfpga_vining_fpga_defconfig
+++ b/configs/socfpga_vining_fpga_defconfig
@@ -47,6 +47,8 @@  CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
 CONFIG_DFU_SF=y
@@ -76,6 +78,7 @@  CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_SOCFPGA=y
 CONFIG_MII=y
 CONFIG_DM_RESET=y
 CONFIG_SPI=y